Semiconductor Insulating Layer Stack for STI-Safe Word Line Etching
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to maintain the integrity of the Shallow Trench Isolation (STI) structure, particularly as the critical dimension of semiconductor devices approaches the 28 nm node and below. Traditional dry etching and wet cleaning methods often damage the STI structure, leading to defects such as edge leakage and reduced reliability and yield of the semiconductor device.
Innovation Solution
A method for manufacturing a semiconductor device involves forming WL structures and STI structures in an array region, creating grooves over the WL structures, and depositing multiple insulating layers with different etch rates. These insulating layers are strategically removed in sequence, with the lower layer acting as an etch stop for the upper layer, while preserving the insulating layers in the grooves to minimize damage to the STI structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional dry etching and wet cleaning methods are used to form buried Word Line structures, then the manufacturing process can be completed, but the STI structure is damaged and edge leakage occurs
Solution Approach 1:
The patent segments the insulating layer into multiple layers with different etch rates. By depositing at least two insulating layers (first insulating layer with higher etch rate, second insulating layer with lower etch rate), the etching process can be controlled to remove material selectively without damaging the STI structure. This segmentation allows the etching to stop at the STI interface, preventing the edge leakage problem.
Solution Approach 2:
The patent changes the etch rate parameter by using insulating layers with different etch rates under the same etching condition. The first insulating layer has a higher etch rate than the second insulating layer, which creates a controlled etching progression. This parameter change enables selective removal of insulating material while preserving the STI structure, resolving the contradiction between process completion and structure integrity.
2Reliability
If multiple insulating layers are deposited and selectively removed, then damage to STI structure is reduced, but the manufacturing process complexity increases
Solution Approach 1:
The patent uses parameter changes (different etch rates of insulating layers) to achieve selective removal. This approach, while adding layers, simplifies the overall process control because the etching automatically stops when it reaches the slower-etching layer, providing self-limiting behavior that reduces the need for complex process monitoring and adjustment.
Solution Approach 2:
The multi-layer insulating structure provides self-service by using the etch rate difference between layers to automatically control the etching depth. The first insulating layer etches faster and is removed first, then the second insulating layer etches slower and stops at the STI interface. This self-regulating mechanism reduces the need for external process control, offsetting the added structural complexity.
3Reliability
If insulating layers are removed in sequence with etch stop layers, then edge leakage is minimized, but the manufacturing time increases
Solution Approach 1:
The patent changes the etch rate parameter to enable selective removal of insulating layers. The first insulating layer with higher etch rate is removed faster, and the second insulating layer with lower etch rate is removed more slowly and stops at the STI interface. This parameter-based selective removal prevents edge leakage while maintaining reasonable manufacturing time by avoiding the need for multiple separate etching steps with different chemistries.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces damage to the STI structure, enhances the performance and yield of the semiconductor device, and minimizes the risk of edge leakage by maintaining the structural integrity of the STI and ensuring that the insulating layers are flush with the semiconductor substrate surface.
Implementation Method 1
depositing at least two insulating layers on a surface of the semiconductor substrate
Implementation Method 2
depositing at least two insulating layers on a surface of the semiconductor substrate
Implementation Method 3
each of the insulating layer has a different etch rate under a same etching condition; the lower insulating layer in the adjacent insulating layers is an etch stop layer of the upper insulating layer
Data Source
AI summary
A semiconductor device manufacturing method includes: providing a semiconductor substrate, wherein the semiconductor substrate includes an array region and a peripheral region; word line structures and shallow trench isolation structures are formed in the array region, grooves are formed over word line structures, and a shallow trench isolation structure is formed in the peripheral region; depositing at least two insulating layers on a surface of the semiconductor substrate, each of the insulating layer has a different etch rate under a same etching condition; and removing part of the insulating layers located on surfaces of the array region and the peripheral region in sequence, wherein a lower insulating layer in the adjacent insulating layers is an etch stop layer of an upper insulating layer, and keeping all the insulating layers in the grooves located over the word line structures.