STI Sidewall Segmentation for UTBB Divot Prevention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Ultra-thin Body and Buried Oxide (UTBB) semiconductor devices face electrical shorting issues due to divots at the interface of shallow trench isolation (STI) regions and source/drain regions, which conventional processing operations like HF cleaning and CMP steps exacerbate, leading to instability in the STI structure.
Innovation Solution
The implementation of a nitride layer lining the bottom portion of the STI sidewall and a hafnium oxide layer lining the top portion, with an insulating material like silicon dioxide within these layers, configured to withstand CMP and HF processing, ensuring the nitride layer terminates below the buried oxide layer and the oxide layer extends above it, reducing electrical shorting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional STI processing operations are used, then manufacturing simplicity is maintained, but divots form at the STI interface causing electrical shorting
Solution Approach 1:
The STI liner is segmented into multiple layers: a bottom nitride layer and an upper oxide layer, each providing different protective functions. This segmentation allows the structure to prevent divot formation and electrical shorting while maintaining manufacturing feasibility through sequential deposition processes.
Solution Approach 2:
The STI structure uses composite materials combining nitride and oxide layers. The nitride layer provides chemical stability and divot prevention, while the oxide layer provides electrical isolation. This composite approach resolves the contradiction by achieving reliable electrical isolation without requiring overly complex processing operations.
2Reliability
If the nitride layer extends above the buried oxide layer, then interface protection is enhanced, but threshold voltage control is compromised
Solution Approach 1:
The nitride layer is positioned locally at the bottom portion of the STI sidewall, directly adjacent to the substrate, where it provides maximum interface protection. The upper oxide layer then provides electrical isolation without interfering with the back bias application needed for threshold voltage tuning. This localized placement resolves the contradiction between interface protection and voltage control.
3Length of moving object
If thinner BOX is used for better scaling, then scaling capability is improved, but susceptibility to processing-induced divots increases
Solution Approach 1:
The bottom nitride layer is deposited beforehand to cushion and protect the interface between the ultra-thin BOX and substrate from processing-induced divots. This preventive measure allows the use of thinner BOX for scaling while maintaining interface integrity and preventing electrical shorting that would otherwise occur with thin BOX structures.
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one STI region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include a nitride layer lining a bottom portion of the sidewall surface, an oxide layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.