STI Stress Implantation in ETSOI for Higher Drive Current
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Solution Overview
Problem
Existing ETSOI devices suffer from lower drive current and degraded performance due to the lack of effective stress generation in the transistor body, particularly with planar structures and thin semiconductor layers.
Innovation Solution
Selective ion implantation into the shallow trench isolation (STI) regions of NMOS/PMOS devices to introduce tensile or compressive stress, using different ion species and temperatures, without adding new masks, to enhance device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If planar structures and thin semiconductor layers are used in ETSOI devices, then device scaling and integration density are improved, but drive current and performance are degraded due to lack of effective stress generation
Solution Approach 1:
The patent applies selective stress to different regions of the device by implanting ions into specific isolation regions while leaving other regions untouched. This creates local quality variations where stressed regions provide enhanced drive current while maintaining the overall planar structure and thin layer configuration for high integration density.
Solution Approach 2:
The patent changes the stress parameter in the isolation regions through ion implantation, transforming the mechanical properties of these regions. By controlling ion species, energy, and temperature, the stress state is modified to generate effective stress in the transistor body, thereby improving drive current without altering the fundamental planar architecture.
2Stress or pressure
If traditional stress elements like embedded SiGe source/drain and dual stress liner are used, then some stress is provided to the transistor body, but high effective stress is not generated due to the extremely thin transistor body and planar structure
Solution Approach 1:
The patent uses isolation regions as intermediary structures to transmit stress to the transistor body. Instead of directly stressing the thin transistor body through conventional means, the ion-implanted isolation regions act as stress mediators that generate effective stress in the transistor body, overcoming the limitations imposed by the extremely thin layer and planar structure.
Solution Approach 2:
The patent transitions from in-plane stress elements (source/drain, liners) to vertical stress generation through ion implantation into isolation regions. This dimensional shift allows stress to be applied from the isolation region depth into the transistor body, creating effective stress that traditional planar stress elements cannot achieve in ETSOI devices.
3Power
If selective ion implantation into STI regions is performed to generate stress, then drive current and device performance are enhanced, but additional process steps and potential mask layers are required
Solution Approach 1:
The patent makes the ion implantation process selective through existing mask structures rather than requiring dedicated stress-generation masks. The same masking infrastructure used for other device fabrication steps is leveraged to define isolation regions for ion implantation, thereby achieving stress generation without adding new mask layers and reducing overall process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Improves transistor performance by optimizing stress levels, enhancing drive current and overall device efficiency without additional mask layers.
Implementation Method 1
modifying a stress of a material of the first isolation region by implanting the first isolation region of the plurality of isolation regions
Data Source
AI summary
Disclosed herein are approaches for forming a shallow trench isolation (STI) to improve extremely thin silicon on insulator (ETSOI) device performance. In one approach, a method may include providing a device stack comprising a buried oxide (BOX) layer in a substrate, patterning a hardmask over the substrate, and forming a plurality of isolation regions in the device stack, wherein the plurality of isolation regions extend through the box layer and the substrate. The method may further include forming a well mask over the device stack, wherein an opening through the well mask exposes a first isolation region of the plurality of isolation regions, and modifying a stress of a material of the first isolation region by implanting the first isolation region of the plurality of isolation regions.