STI Trench Insulation Layout for Height and Deposition Control
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Solution Overview
Problem
In semiconductor devices like DRAM, the level difference between the STI surface and the memory cell array region needs to be minimized, while the STI surface should protrude from the peripheral circuit region to prevent conducting material accumulation during gate dielectric film preprocessing.
Innovation Solution
The semiconductor device design includes an STI region with insulating films embedded in trenches, where the inner walls of the trenches on the peripheral circuit side are covered with insulating films to prevent exposure and material accumulation, while ensuring the STI surface protrudes from the peripheral circuit region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the STI surface is made to protrude from the peripheral circuit region, then conducting material accumulation is prevented, but the level difference between STI and memory cell array region increases
Solution Approach 1:
The patent applies different surface heights to different regions: the STI region in the peripheral circuit area protrudes to prevent material accumulation, while the STI region in the memory cell array area maintains a lower level to minimize level differences. This local differentiation resolves the contradiction by allowing the STI to serve different functional requirements in different locations.
Solution Approach 2:
The STI structure is segmented into multiple regions with different height characteristics. The peripheral circuit region STI protrudes from the surface, while the memory cell array region STI remains at or below the surface level. This segmentation allows each region to optimize for its specific functional requirements without compromising the other.
2Manufacturing precision
If the STI surface is kept level with the memory cell array region, then level difference is minimized, but conducting material accumulates on the exposed inner wall of STI in peripheral circuit region
Solution Approach 1:
The patent implements local quality differentiation where the STI surface height varies by region. In the peripheral circuit region, the STI protrudes to prevent material accumulation, while in the memory cell array region, the STI maintains a lower level to minimize overall level differences. This resolves the contradiction by allowing each region to optimize for its specific requirements.
Solution Approach 2:
The STI structure is divided into segmented regions with different height characteristics. The peripheral circuit STI segment protrudes above the surface to prevent conducting material accumulation, while the memory cell array STI segment remains at or below surface level. This segmentation enables simultaneous satisfaction of both contradictory requirements in different locations.
3Reliability
If the inner wall of STI is exposed in peripheral circuit region, then material accumulation occurs during gate dielectric preprocessing, but covering the inner wall increases device complexity
Solution Approach 1:
The patent applies local quality by making the STI protrude only in the peripheral circuit region where material accumulation is a problem, while keeping the STI level in the memory cell array region. This targeted approach prevents material accumulation without unnecessarily increasing device complexity across the entire structure.
Solution Approach 2:
The STI structure is segmented such that only the peripheral circuit region STI protrudes to prevent material accumulation, while the memory cell array region STI remains at standard level. This selective segmentation prevents material accumulation problems without adding complexity to regions where it is not needed.
Data Source
AI summary
An example apparatus includes a semiconductor substrate including first and second circuit regions, a first trench extending in a first direction and formed between the first and second circuit regions, wherein the first trench includes a first inner wall positioned on the first circuit region side and a second inner wall positioned on the second circuit region side, and a plurality of second trenches extending in a second direction different from the first direction and formed in the first circuit region such that the second trench communicates with the first trench at the first inner wall; and a first insulating film formed on the first and second inner walls such that the second inner wall is covered with the first insulating film without being exposed.