STI Trench Capacitor Structure for Longer Memory Retention
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Solution Overview
Problem
Current memory technologies, such as eDRAM, face challenges with low retention time and high energy consumption due to rapid current leakage, requiring frequent refresh operations, while SRAM offers better speed and reliability but at the cost of higher transistor count and power consumption.
Innovation Solution
The implementation of shallow-trench-isolation (STI) regions and fin-cut regions for depositing metal-dielectric-metal structures enhances stored charge capacity, allowing for increased retention times and improved soft-error rate robustness by forming capacitors that are CMOS-compatible, thereby boosting storage node capacitance and charge capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If eDRAM is used for memory storage, then area and transistor count are reduced, but retention time decreases and energy consumption increases due to rapid current leakage
Solution Approach 1:
The patent transitions from planar capacitor structures to three-dimensional trench-based capacitor structures. By etching trenches into the substrate and forming capacitors within these vertical structures, the storage volume is increased without proportionally increasing the planar area, thereby improving retention time while maintaining area efficiency.
Solution Approach 2:
The patent employs composite material structures for the capacitor, including metal-dielectric-metal configurations and trench liners. These composite structures optimize both the capacitance density and the electrical isolation properties, reducing leakage current while maximizing storage capacity within the available area.
2Reliability
If SRAM is used for memory storage, then speed and reliability are improved, but transistor count and power consumption increase
Solution Approach 1:
The patent develops a universal memory cell architecture that can operate in different modes (SRAM-like or eDRAM-like) by configuring the trench capacitor structures. This multi-functional design allows the same basic cell structure to provide both the speed/reliability of SRAM and the area efficiency of eDRAM, reducing the need for separate specialized structures.
3Quantity of substance
If trench capacitors are formed in substrate regions, then storage node capacitance is boosted, but manufacturing complexity increases
Solution Approach 1:
The patent combines the formation of isolation trenches and capacitor trenches into a single etching process step. By merging these two previously separate manufacturing steps into one, the patent reduces process complexity while achieving both electrical isolation and enhanced capacitance storage in the same substrate regions.
Solution Approach 2:
The patent segments the substrate into distinct regions with different trench depths and configurations. By dividing the substrate处理 into manageable segments (shallower trenches for isolation, deeper trenches for capacitance storage), the manufacturing process becomes more controllable and less complex, allowing precise capacitance tuning without overwhelming process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a '2×' improvement in storage node capacitance and retention time for eDRAM, and a greater than '2×' improvement in soft-error rate for SRAM, addressing the limitations of existing memory technologies.
Implementation Method 1
forming capacitors that are CMOS-compatible, thereby boosting storage node capacitance and charge capacity
Data Source
AI summary
According to one implementation of the present disclosure, a circuit structure is configured to store charge in a charge-based storage element, where the charge-based storage element is disposed at least partially in a shallow-trench-isolation (STI) region of the circuit. According to one implementation of the present disclosure, a method includes: providing a circuit structure disposed on a substrate and a shallow-trench-isolation (STI) region of a circuit; forming an opening of the substrate and the STI region by removing a portion of the substrate and STI region; placing a first liner material in the opening and on remaining portions of the substrate and the STI region; and depositing a first metal layer in the opening on the first liner material.