Shallow Trench Isolation Divot Mitigation via Epitaxial Buffer
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Solution Overview
Problem
Shallow Trench Isolation (STI) structures in semiconductor manufacturing lead to divots during planarization, causing high leakage current and performance degradation of semiconductor devices, especially as device dimensions scale down.
Innovation Solution
A method involving the formation of a first trench filled with an epitaxial layer, followed by a second trench with a narrower width, both filled with dielectric layers, where the epitaxial layer's surface is higher than the substrate, reducing divot dimensions and stress, thereby improving semiconductor device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If a shallow trench is filled with dielectric material and planarized by CMP, then the substrate surface is flattened, but downward depressions (divots) are formed at the interface between the dielectric material and substrate
Solution Approach 1:
An epitaxial layer is formed in advance within the shallow trench before filling with dielectric material. This preliminary action creates a stress-compensating structure that prevents divot formation during subsequent CMP planarization, while maintaining overall surface flatness
Solution Approach 2:
The patent uses a composite structure combining epitaxial layer (semiconductor material) and dielectric material in the shallow trench. This composite configuration allows the epitaxial layer to provide mechanical support and stress management, preventing the dielectric-substrate interface from forming divots during planarization
2Productivity
If device dimensions are scaled down, then device density increases, but the relative size of divots becomes larger, causing more serious performance degradation
Solution Approach 1:
The epitaxial layer is formed in advance within the shallow trench to create a stress-compensating structure that prevents divot formation, thereby maintaining interface flatness and device performance even as device dimensions are scaled down and device density increases
3Quantity of substance
If divots are formed at the dielectric-substrate interface, then leakage current increases, but device performance degrades
Solution Approach 1:
The composite structure of epitaxial layer and dielectric material in the shallow trench maintains interface flatness and prevents divot formation, thereby reducing leakage current paths and improving device performance reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes the negative effects of divots on semiconductor device performance by reducing divot dimensions and applying stress through material differences, enhancing the performance of MOS transistors.
Implementation Method 1
forming an epitaxial layer in the first trench
Data Source
AI summary
The invention provides a STI structure and a method for manufacturing the same. The STI includes a semiconductor substrate; a first trench formed on the upper surface of the semiconductor substrate and filled with an epitaxial layer, wherein the upper surface of the epitaxial layer is higher than that of the semiconductor substrate; and a second trench formed on the epitaxial layer and filled with a first dielectric layer, wherein the upper surface of the first dielectric layer is flush with that of the epitaxial layer, and the width of the second trench is smaller than that of the first trench. The invention reduces the influences of divots on performance of the semiconductor device.