Stiffener Basket Semiconductor Package for Low-Height DRAM Layout
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Solution Overview
Problem
Conventional semiconductor packages face challenges due to the differing heights of DRAM devices and other electrical components, leading to increased package height, complex thermal management, and signal transmission issues.
Innovation Solution
A semiconductor package design featuring a stiffener with a basket portion that allows DRAM devices to be placed horizontally adjacent to the package substrate, reducing vertical size and facilitating even heat distribution, along with shorter wire connections for improved signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DRAM devices are mounted on top of the package substrate next to other electrical components, then computing performance is improved, but package height increases due to the height of the DRAM devices
Solution Approach 1:
The patent transitions from vertical stacking (3D stacking) to horizontal placement (2D arrangement) of DRAM devices on the package substrate. This dimensional change allows multiple DRAM devices to be arranged side-by-side rather than stacked vertically, thereby maintaining high computing performance while reducing overall package height to be substantially flush with other electrical components.
2Productivity
If DRAM devices are mounted on the package substrate, then computing performance is improved, but thermal management becomes more difficult due to size differences between DRAM devices and electrical components
Solution Approach 1:
The patent creates a substantially flush surface by placing DRAM devices horizontally adjacent to the package substrate, aligning their top surfaces with other electrical components. This equipotential surface enables uniform heat distribution and simplifies thermal management by allowing consistent thermal interface materials and heat sinks to be applied across all components without accommodating height variations.
3Reliability
If DRAM devices are connected to the package substrate using wires, then signal transmission is achieved, but signal transmission quality deteriorates due to long wire lengths
Solution Approach 1:
The patent extracts and eliminates the wire interconnection layer from the traditional vertical stacking architecture. By placing DRAM devices horizontally adjacent to the package substrate with direct contact, the design removes the need for long wire bonds or through-silicon vias that previously connected vertically stacked components, thereby reducing signal transmission loss and improving signal integrity.
Data Source
AI summary
A semiconductor package is provided including: a package substrate with a top surface, wherein the top surface extends to a peripheral side surface of the package substrate; a stiffener with a lateral portion and a basket portion, wherein the lateral portion is positioned over the top surface of the package substrate and the basket portion overhangs from the top surface of the package substrate adjacent to the peripheral side surface of the package substrate; at least one semiconductor die positioned in the basket portion of the stiffener; and at least one wire attached to the at least one semiconductor die and extending out of the basket portion of the stiffener.