Signal Electromigration Analysis via Partitioned Stimulus Vectors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current circuit models oversimplify signal electromigration analysis, leading to overestimation of effects and potential catastrophic failures due to reduced component density and overlooked signal combinations, resulting in costly re-designs and manufacturing disruptions.
Innovation Solution
A method involving partitioning of integrated circuit netlists into smaller partitions for parallel computation in a cloud environment, using stimulus vectors to induce current flows and identify electromigration effects, thereby reducing computational burden and enhancing analysis accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If circuit models simplify the assumptions of signal flow to reduce computational complexity, then computational burden is reduced, but signal electromigration effects are overestimated leading to conservative design decisions
Solution Approach 1:
The patent divides the circuit into partitions and identifies specific logic paths within those partitions. By segmenting the analysis to focus only on relevant paths and components, the computational complexity is reduced while maintaining accurate SEM analysis for critical areas, avoiding the need to simplify assumptions across the entire circuit.
2Reliability
If component density is reduced to account for overestimated sem effects, then reliability is improved, but cost efficiency of circuit fabrication deteriorates
Solution Approach 1:
The patent applies different analysis rigor to different parts of the circuit by identifying specific logic paths and delay arcs. Critical paths receive detailed SEM analysis while non-critical areas use simplified models, allowing high component density in non-critical areas and targeted reinforcement only where needed, thus maintaining reliability without sacrificing overall fabrication efficiency.
3Reliability
If exhaustive signal combinations are analyzed to prevent catastrophic failure, then reliability is improved, but computational burden increases significantly
Solution Approach 1:
The patent performs preliminary identification of logic paths and delay arcs before conducting SEM analysis. By pre-processing the circuit to identify only relevant paths that could experience SEM effects, the analysis is focused on critical areas only, preventing catastrophic failures through targeted analysis rather than exhaustive analysis of all possible signal combinations.
Data Source
AI summary
A method for obtaining a partition netlist from a partition of an integrated circuit netlist and identifying a logic path from an input to an output in the partition netlist is provided. The method includes identifying a first delay arc for the logic path including circuit components from the partition netlist, and configuring a first input stimulus vector to invert the input in the partition netlist and to induce a current through at least one of the plurality of circuit components. When a second input stimulus vector is associated with a second delay arc that is equivalent to the first delay arc in the logic path, the method includes selecting one of the first or second input stimulus vectors for a set of input stimuli vectors. The method further includes determining an electromigration effect on the partition netlist with the input stimuli vectors.