Shallow Trench Isolation Capacitor for Noise Reduction
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Solution Overview
Problem
Current semiconductor fabrication processes are unable to form planar decoupling capacitors with adequate decoupling capacitance to effectively protect integrated circuits from current and voltage noise without consuming large amounts of valuable circuit area.
Innovation Solution
The method involves fabricating decoupling capacitor structures in shallow trench isolation trenches, where the bottom plate is formed from the substrate and the top plate is recessed below the channel region, with a thicker dielectric layer on the sidewalls and a thinner layer on the bottom to minimize sidewall capacitance and isolate the capacitor from adjacent active device operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar decoupling capacitors are formed with larger area to achieve adequate decoupling capacitance, then noise protection capability is improved, but circuit area consumption increases
Solution Approach 1:
The patent transitions from planar capacitors to three-dimensional trench capacitors by etching deep trenches into the substrate and forming capacitor plates vertically within the trench structure. This vertical dimensionality change enables significantly higher capacitance density, achieving adequate decoupling capacitance without proportionally increasing the horizontal circuit area footprint.
Solution Approach 2:
The capacitor structure is nested within the shallow trench isolation region, utilizing the existing trench infrastructure. The bottom capacitor plate is formed at the trench bottom, the dielectric layer is deposited to line the trench walls, and the top capacitor plate is formed above, creating a nested configuration that maximizes capacitance within the available vertical space of the isolation region.
2Reliability
If thicker dielectric layer is formed on sidewalls to isolate capacitor from adjacent active devices, then electrical isolation is improved, but manufacturing complexity increases
Solution Approach 1:
The dielectric layer is formed with non-uniform thickness, being thicker on the trench sidewalls and thinner on the trench bottom. This local quality variation is achieved through controlled deposition processes that exploit the trench geometry, providing enhanced electrical isolation on the sidewalls where it is most needed for separating adjacent active devices, while maintaining adequate capacitance through the bottom region.
Data Source
AI summary
A semiconductor process and apparatus provide a shallow trench isolation capacitor structure that is integrated in an integrated circuit and includes a bottom capacitor plate that is formed in a substrate layer (10) below a trench opening, a capacitor dielectric layer (22) and a recessed top capacitor plate (28) that is covered by an STI region (30) and isolated from cross talk by a sidewall dielectric layer (23).