STI Structure for CMOS Image Sensors Using Two-Step Epitaxial Growth
Solution Overview
Problem
Current shallow trench isolation (STI) techniques in CMOS image sensors face challenges with increased dark current due to silicon dangling bonds, especially in high-temperature environments, and boron ion-implantation methods compromise full well capacity and isolation resolution.
Innovation Solution
The implementation of a two-step epitaxial growth process to form a shallow trench isolation structure, where an un-doped semiconductor layer is grown to reduce trench depth and width, followed by a doped layer to fill the trench and form a protrusion, eliminating silicon dangling bonds and enhancing boron isolation resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shallow trench isolation (STI) is used to isolate pixels and devices, then device isolation is improved, but silicon dangling bonds on trench walls and bottom increase dark current
Solution Approach 1:
A thin film layer (first material layer) is introduced as an intermediary between the silicon substrate and the STI structure. This layer acts as a mediator that prevents direct contact between silicon dangling bonds and the STI structure, thereby reducing trap-assisted tunneling and dark current while maintaining effective device isolation
Solution Approach 2:
The isolation structure is formed as a composite consisting of multiple materials: the silicon substrate, the thin film layer (first material layer), and the STI material. This composite structure combines the isolation benefits of STI with the protective properties of the thin film layer, achieving both good isolation and reduced dark current
2Measurement precision
If pixel size is reduced to increase the number of pixels on a wafer, then resolution is improved, but device isolation becomes more difficult and dark current increases
Solution Approach 1:
The thin film layer is selectively applied only in the trench regions where isolation is needed, providing localized protection against dark current. This allows pixel size to be reduced for higher resolution while maintaining effective isolation in the critical trench areas without adding unnecessary material to the entire pixel area
3Object-generated harmful factors
If boron implantation is used to passivate STI-Si interface, then dark current is reduced, but boron diffuses into silicon and reduces photodiode area and full well capacity
Solution Approach 1:
The thin film layer serves as a physical barrier that prevents boron atoms from diffusing into the silicon substrate. This intermediary layer allows boron to be used for passivation at the STI interface without the harmful lateral diffusion that would otherwise reduce photodiode area and full well capacity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces dark current, maintains high full well capacity, and provides a more graded junction, improving the overall performance and resolution of CMOS image sensors.
Implementation Method 1
a first layer of un-doped semiconductor material epitaxially grown in the trench
Implementation Method 2
a second layer of doped semiconductor material epitaxially grown on the first layer, the second layer filling the trench and forming a protrusion above the front-side of the semiconductor substrate
Data Source
AI summary
A shallow trench isolation (STI) structure and method of fabrication includes a two-step epitaxial growth process. A trench larger than the target STI structure is etched into a semiconductor substrate, a first layer of un-doped semiconductor material epitaxially grown in the trench to provide an STI structure having a target depth and a critical dimension, and a second layer of doped semiconductor material epitaxially grown on the first layer, said second layer filling the trench and forming a protrusion above the front-side of the semiconductor substrate.