Shallow Trench Isolation High-k Dielectric Planarity
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Solution Overview
Problem
Shallow trench isolation (STI) technology in semiconductor manufacturing faces challenges such as dishing due to chemical-mechanical polishing, leading to open circuits from metal interconnect collapse or breaks, and issues with surface planarity and high-frequency performance.
Innovation Solution
The method involves depositing a high-k material layer in trenches with larger surface areas to improve surface planarity and reduce eddy currents, enhancing high-frequency performance by using a sequence of patterned photoresist layers, dielectric layers, and chemical-mechanical polishing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical-mechanical polishing is used to planarize the trench surface, then surface planarity is improved, but dishing occurs in low pattern density regions causing metal interconnect collapse or breaks
Solution Approach 1:
The patent applies preliminary action by performing an oxide-reduction etching step before chemical-mechanical polishing. This pre-treatment removes excess oxide material from the trench surface, reducing the polishing load and preventing over-polishing that causes dishing. The etching step prepares the surface in advance, allowing the subsequent CMP to achieve planarity without removing excessive material that would lead to metal interconnect failure.
Solution Approach 2:
The patent changes the physical-chemical parameters of the trench surface by controlling the oxide layer thickness and composition through the etching process. By adjusting etching conditions (time, chemistry, temperature), the oxide layer is reduced to optimal thickness, which modifies the surface properties to be more amenable to controlled polishing, thereby preventing dishing while maintaining planarity.
2Reliability
If conventional STI processing is used, then transistor isolation is achieved, but surface planarity deteriorates due to dishing in low pattern density regions
Solution Approach 1:
The oxide-reduction etching step serves as a preliminary action that prepares the trench surface before CMP processing. By removing excess oxide in advance, the surface topology is optimized, ensuring that subsequent polishing produces uniform planarity across both high and low pattern density regions, thereby resolving the dishing problem while maintaining effective transistor isolation.
Solution Approach 2:
The process incorporates feedback control through monitoring the trench surface condition after etching and adjusting CMP parameters accordingly. The etching step creates a controlled surface state that provides feedback information about the oxide distribution, allowing optimization of polishing parameters to achieve uniform planarity across varying pattern densities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents dishing and metal interconnect failures, improves surface planarity, reduces thermal issues by lowering eddy currents, and enhances high-frequency performance in semiconductor devices.
Implementation Method 1
chemical-mechanical polishing (CMP) with different pattern densities may result in over-polishing to cause dishing in the trench in the low pattern density region
Data Source
AI summary
Shallow trench isolation structures in a semiconductor device and a method for manufacturing the same. The method includes steps hereinafter. A substrate is provided with a pad oxide layer and a first patterned photoresist layer thereon. A first trench is formed in the substrate corresponding to the first patterned photoresist layer. A first dielectric layer is deposited in the first trench and on the substrate. A second patterned photoresist layer is provided to form an opening in the first dielectric layer and a second trench in the substrate corresponding to the second patterned photoresist layer. A second dielectric layer is deposited to cover the first trench and the second trench in the substrate and the first dielectric layer on the substrate. The second dielectric layer is removed by chemical-mechanical polishing until the first dielectric layer is exposed. The first dielectric layer on the substrate is selectively removed.