Shallow Trench Isolation Liner and Fill Process for FinFET Protection
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Solution Overview
Problem
Current fin-based field effect transistor (FinFET) integration schemes using enhanced High Aspect Ratio Process (eHARP) for shallow trench isolation (STI) gap fill suffer from poor film density, leading to severe STI-oxide recess and fin damage, resulting in poor device performance.
Innovation Solution
The implementation of multiple protective liners, including an in-situ steam generation (ISSG)-based first liner layer and silicon nitride (SiN) or poly-silicon second liner layer, followed by an enhanced high aspect ratio process (eHARP) fill and subsequent polishing, etching back, and refilling with high density plasma (HDP) material, with optional silicon deposition for additional protection during downstream processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If eHARP process is used for STI gap fill, then trench filling is achieved, but film density is poor leading to STI-oxide recess and fin damage
Solution Approach 1:
The patent divides the STI formation process into multiple sequential steps with different fill materials (eHARP followed by HDP), where each step addresses specific requirements. The eHARP step provides initial trench filling while the subsequent HDP step provides high-density refill, thereby resolving the contradiction between achieving gap fill and ensuring film density.
Solution Approach 2:
The patent employs a composite approach by combining two different fill materials (eHARP material and HDP material) in sequence. Each material contributes its strengths: eHARP for aspect ratio handling and HDP for high density, together creating a composite STI structure that overcomes the limitations of using either material alone.
2Device complexity
If single liner layer is used, then process complexity is low, but etch stopping and protection is insufficient
Solution Approach 1:
The patent segments the liner structure into multiple functional layers (first liner layer and second liner layer), where each layer provides specific protection functions. This segmentation enables sufficient etch stopping and fin protection while maintaining a systematic approach to the increased complexity.
Solution Approach 2:
The patent applies liner layers beforehand to provide protective cushioning during subsequent etching and processing steps. The liners are deposited in advance to prevent fin damage and provide etch stopping, thereby protecting critical structures before harmful processes occur.
3Productivity
If no protective liner is used, then process steps are reduced, but fin damage occurs during downstream wet etch processes
Solution Approach 1:
The patent introduces liner layers as intermediary protective structures between the fin structures and harmful wet etch processes. These liners act as mediators that prevent direct contact between etchants and fins, thereby eliminating fin damage while allowing downstream processing to proceed.
Solution Approach 2:
The protective liner layers are deposited beforehand to provide cushioning protection against subsequent wet etch processes. This prior protection enables safe execution of downstream processing steps that would otherwise cause fin damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the etch stopping and removal rates, reducing fin damage and improving device performance by providing effective protection and density in the STI layer formation.
Implementation Method 1
a first liner layer (e.g., an in-situ steam generation (ISSG)-based layer)
Implementation Method 2
refilling the set of trenches with a high density plasma (HDP) material
Data Source
AI summary
Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.