Shallow Trench Isolation Planarization for Leakage Control
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Solution Overview
Problem
Existing methods for forming shallow trench isolation structures in semiconductor substrates after gate stack formation introduce undesirable effects such as divot expansion, leakage paths, and variability in device performance due to interactions with embedded source and drain regions, leading to issues like increased threshold voltage variability and leakage current.
Innovation Solution
A method involving the formation of a gate stack with a dielectric and electrode on a semiconductor substrate, followed by creating trenches surrounding semiconductor portions and filling them with a dielectric material to form shallow trench isolation structures, which minimizes divot formation and ensures physical contact with the gate electrode, thereby reducing leakage and performance variability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shallow trench isolation structures are formed using conventional methods, then lateral electrical isolation is provided, but divots form around boundaries and expand in preclean or wet etch steps to create leakage paths
Solution Approach 1:
The patent performs preliminary planarization of the semiconductor substrate surface before forming the shallow trench isolation structures. This preliminary action removes potential divot formation sites and creates a flat surface, preventing subsequent leakage path formation during preclean or wet etch steps while maintaining electrical isolation functionality
Solution Approach 2:
The patent applies a preliminary anti-action by performing surface planarization and forming protective layers before the shallow trench isolation formation process. This counteracts the potential harmful effect of divot formation by creating a uniform surface that prevents etch attack and leakage path development
2Productivity
If embedded Si:C source and drain regions are formed to increase on-current, then device performance improves, but facets form at the interface with shallow trench isolation structures causing threshold voltage variability
Solution Approach 1:
The patent performs preliminary planarization of the semiconductor substrate surface before forming embedded source and drain regions. This creates a uniform baseline that prevents facet formation at the interface between the embedded regions and shallow trench isolation structures, thereby reducing threshold voltage variability while preserving the on-current enhancement benefit
Solution Approach 2:
The patent changes the surface topology parameter by planarizing the substrate before embedded region formation. This parameter change eliminates the geometric discontinuities that would otherwise create facets, ensuring uniform interfaces and consistent threshold voltage across devices
3Productivity
If shallow trench isolation structures are subjected to thermal anneals at temperatures greater than 700° C. for dopant activation, then dopant activation is achieved, but dopants diffuse to boundaries and increase leakage current
Solution Approach 1:
The patent performs preliminary planarization and forms protective structures before thermal annealing. This preliminary preparation creates a configuration where dopants are activated effectively but diffusion to isolation boundaries is minimized due to the uniform surface geometry and protective layering, thereby reducing leakage current
Solution Approach 2:
The patent introduces intermediate protective layers and planarized surfaces that act as mediators during thermal annealing. These intermediaries allow dopant activation to proceed while preventing direct diffusion pathways to the shallow trench isolation boundaries, thus activating dopants without increasing leakage
4Ease of manufacture
If conventional shallow trench isolation formation is performed, then isolation structures are created, but variability in printed lithographic images occurs as a function of underlying shallow trench isolation region density
Solution Approach 1:
The patent performs preliminary planarization of the semiconductor substrate surface before forming shallow trench isolation structures. This preliminary action creates a uniform surface topology that eliminates density-dependent variations in lithographic image printing, ensuring consistent patterning across different regions regardless of underlying isolation structure density
Data Source
AI summary
Doped wells, gate stacks, and embedded source and drain regions are formed on, or in, a semiconductor substrate, followed by formation of shallow trenches in the semiconductor substrate. The shallow trenches can be formed by forming a planarized material layer over the doped wells, the gate stacks, and the embedded source and drain regions; patterning the planarized material layer; and transferring the pattern in the planarized material layer into the gate stacks, embedded source and drain regions, and the doped wells. The shallow trenches are filled with a dielectric material to form shallow trench isolation structures. Alternately, the shallow trenches can be formed by applying a photoresist over the doped wells, the gate stacks, and the embedded source and drain regions, and subsequently etching exposed portions of the underlying structures. After removal of the photoresist, shallow trench isolation structures can be formed by filling the shallow trenches.