Shallow Trench Isolation with Rounded Corners
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Solution Overview
Problem
Conventional shallow trench isolation (STI) and local oxidation of silicon (LOCOS) techniques face limitations such as silicon area consumption, non-planar surface topology, and high defect density in insulating materials due to mechanical and thermal stresses, leading to reduced electrical isolation effectiveness, especially in densely-packed integrated circuits.
Innovation Solution
The method involves etching trenches with a rounded profile and conformally depositing a dielectric layer, followed by selective oxidation using an in situ steam generated (ISSG) process to create a variable-thickness silicon nitride layer with reduced stress, resulting in a modified sidewall oxide layer with rounded corners, which reduces dislocation density in the insulating material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional STI trenches with sharp corners are formed, then the trench width can be reduced, but the dislocation density in the insulating material increases due to mechanical and thermal stresses
Solution Approach 1:
The patent applies curvature by rounding the corner portions of the STI trench instead of maintaining sharp corners. This is achieved through a multi-step process: etching trenches with rounded corners, depositing a first dielectric material conformally, performing selective oxidation that creates a variable thickness oxide layer (thinner at corners), and filling with insulating material. The rounded corner geometry reduces stress concentration points, thereby reducing dislocation density in the insulating material while maintaining narrow trench dimensions for high device density.
2Reliability
If LOCOS structures are used for electrical isolation, then electrical isolation between devices is achieved, but substantial silicon active area is consumed and non-planar surface topology is created
Solution Approach 1:
The patent segments the isolation approach by using narrow trenches rather than broad LOCOS regions. The STI structure divides the substrate into isolated regions through precise trench formation, allowing much higher device density compared to LOCOS. The segmented trench approach maintains electrical isolation functionality while consuming minimal active area, enabling densely-packed integrated circuits.
3Productivity
If the width of STI trench is decreased to increase device density, then more devices can be packed, but the insulating material capacity to provide electrical isolation is reduced due to high defect density
Solution Approach 1:
The patent changes the geometric parameters of the trench corner portions from sharp to rounded, and modifies the oxide layer thickness parameter through selective oxidation. This creates a variable thickness profile where the oxide is thinner at rounded corners and thicker on vertical walls. This parameter optimization allows narrow trench widths for high device density while maintaining sufficient insulating capacity by reducing stress-induced defects through the rounded corner geometry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electrical insulation by minimizing defects and stress in the insulating material, allowing for effective isolation even in narrower trenches, thereby improving the reliability of densely-packed integrated circuit devices.
Implementation Method 1
oxidizing the dielectric layer. A portion of the dielectric layer deposited over the corner portion is oxidized at a first oxidization rate, and a portion of the dielectric layer deposited over the upright wall portion is oxidized at a second oxidization rate
Implementation Method 2
selective oxidation using an in situ steam generated (ISSG) process to create a variable-thickness silicon nitride layer with reduced stress
Data Source
AI summary
A method for manufacturing a shallow trench isolation structure comprises etching a plurality of trenches into a silicon substrate. The trenches have an upright wall portion, a bottom floor portion, and a corner portion connecting the upright wall portion and the bottom floor portion. The method further comprises conformally depositing a dielectric layer into the trenches. The dielectric layer covers at least part of the upright wall portion, at least part of the bottom floor portion, and at least part of the corner portion. The method further comprises oxidizing the dielectric layer. A portion of the dielectric layer deposited over the corner portion is oxidized at a first oxidization rate, and a portion of the dielectric layer deposited over the upright wall portion is oxidized at a second oxidization rate. The first oxidization rate is less than the second oxidization rate. The method further comprises depositing an electrically insulating material into the trenches over the dielectric layer.


