Stud Bump Stitch Bonding for Low-Profile High-Voltage Isolation
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Solution Overview
Problem
Close spacing between high voltage isolation barrier components in electronic devices can lead to undesirable dielectric breakdown or arcing, particularly in low profile devices with short loop height restrictions, due to insufficient wire stitch angle in wire bond connections.
Innovation Solution
A packaged electronic device design featuring conductive bond wires with ends bonded to semiconductor dies at angles greater than or equal to 60 degrees, utilizing conductive stud bumps to increase spacing and prevent arcing, while maintaining a low profile and high voltage isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is performed with conventional stitch angles in low profile devices, then device compactness is achieved, but dielectric breakdown and arcing occur due to insufficient spacing
Solution Approach 1:
The patent introduces a vertical dimension by forming stud bumps that extend upward from the capacitor plates. This elevates the wire bond stitch point to a higher Z-position, increasing the effective spacing and stitch angle without increasing the horizontal footprint of the device. The stud bump creates a three-dimensional bonding geometry that resolves the conflict between compactness and voltage isolation.
Solution Approach 2:
The stud bump acts as an intermediary structure between the capacitor plate and the wire bond. It provides an elevated bonding surface that increases the distance between the wire and the lower voltage domain, thereby preventing arcing while maintaining a compact overall device profile. The stud bump mediates the conflict between close spacing and electrical isolation.
2Volume of moving object
If close spacing is used between high voltage isolation barrier components, then device size is reduced, but dielectric breakdown occurs
Solution Approach 1:
By transitioning from a two-dimensional planar bonding approach to a three-dimensional vertical bonding approach using stud bumps, the patent achieves increased electrical spacing without increasing horizontal device dimensions. The wire bonds connect to elevated points on the stud bumps, creating greater vertical separation between voltage domains while maintaining compact device footprint.
Solution Approach 2:
The stud bumps are localized features formed only at specific bonding locations on the capacitor plates. This local modification provides enhanced voltage isolation precisely where needed at the wire bond interfaces, while the rest of the device maintains its compact close-spacing design. The local quality change allows differential treatment of critical bonding regions versus non-critical areas.
Data Source
AI summary
An electronic device includes a bond wire with a first end bonded by a ball bond to a planar side of a first conductive plate, and a second end bonded by a stitch bond to a conductive stud bump at an angle greater than or equal to 60 degrees. A wirebonding method includes bonding the first end of the conductive bond wire to the first conductive plate includes forming a ball bond to join the first end of the conductive bond wire to a planar side of the first conductive plate by a ball bond, and bonding the second end of the conductive bond wire to the conductive stud bump includes forming a stitch bond to join the second end of the conductive bond wire to the conductive stud bump.