Stitch-Chip Microinterconnects for Low-Loss Chiplet RF Links
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Solution Overview
Problem
Conventional packaging technologies face challenges in managing off-chip interconnect losses and transitions at high frequencies, leading to high parasitic inductance, impedance mismatch, and radiation losses, which degrade the electrical performance of wireless systems, and hinder high-performance, dense multi-chiplet integration.
Innovation Solution
The use of stitch-chip architectures with compressible microinterconnects that connect chiplets through a substrate, featuring a ground plane and recesses, allowing for low-loss and broadband interconnects that accommodate different chiplet heights and impedance mismatches, eliminating the need for additional matching networks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire- or ribbon-bonds are used to bridge chiplets, then chiplets can be connected to substrate, but high parasitic inductance and impedance mismatch occur at high frequencies
Solution Approach 1:
The patent extracts the harmful wire- or ribbon-bond interconnects from the system and replaces them with stitch-chiplets that have integrated microinterconnects. This removes the source of parasitic inductance and impedance mismatch, directly resolving the contradiction between achieving reliable electrical connections and avoiding harmful parasitic effects.
Solution Approach 2:
The stitch-chiplet acts as an intermediary component between the substrate and chiplets. Instead of using traditional wire-bonds, the stitch-chiplet provides a new mediation mechanism through its integrated microinterconnects, which have lower parasitic inductance and better impedance matching characteristics.
2Reliability
If matching network is added to improve bandwidth, then electrical performance improves, but device area increases
Solution Approach 1:
The patent extracts and eliminates the need for separate matching networks by integrating the interconnect function directly into the stitch-chiplet. The microinterconnects are designed with inherent impedance control, removing the requirement for additional matching network components and the area they would occupy.
Solution Approach 2:
The patent merges the interconnect function and impedance matching function into a single integrated microinterconnect structure within the stitch-chiplet. This consolidation eliminates the need for separate matching networks, thereby reducing the area between chiplets while maintaining electrical performance.
3Reliability
If conventional packaging is used, then chiplets can be connected, but off-chip interconnect losses and radiation losses increase at high frequencies
Solution Approach 1:
The patent replaces the mechanical wire- or ribbon-bond interconnect system with an integrated microinterconnect system on the stitch-chiplet. This substitution reduces radiation losses and off-chip interconnect losses by providing a more controlled and compact interconnection path, thereby improving signal transmission at high frequencies.
4Productivity
If dense multi-chiplet integration is achieved, then system performance improves, but parasitic effects and impedance mismatch worsen
Solution Approach 1:
The stitch-chiplet serves as an intermediary with optimized microinterconnects that facilitate dense chiplet integration while maintaining impedance control. The integrated interconnect structure reduces impedance mismatch even as integration density increases, allowing high-productivity multi-chiplet systems without exacerbating harmful parasitic effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The stitch-chip architecture achieves superior RF/mm-wave performance with reduced return loss and insertion loss, enabling high-performance, dense multi-chiplet integration and reworkability, while compensating for non-planarity and thermal expansion mismatches.
Implementation Method 1
compressible microinterconnects connecting the frontside of the first chiplet to the frontside of the second chiplet
Data Source
AI summary
A device includes a substrate; first and second chiplets on the substrate, each of the first and second chiplets having a backside and an opposing frontside, wherein the backside of the first and second chiplets faces the substrate; and at least one stitch-chip having compressible microinterconnects connecting the frontside of the first chiplet to the frontside of the second chiplet opposite the substrate.