Semiconductor Stitch Structure for Mask Shift Detection

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Solution Overview

Problem

Photonic devices in integrated circuits face performance issues due to process variation and mask shifts during lithography, leading to waveguide pattern variations and increased stitch loss when optical signals propagate across multiple dies.

Innovation Solution

A semiconductor stitch pattern and structure are introduced to monitor manufacturing operations and mask shifts, allowing for prompt adjustments to mitigate stitch loss by using specific patterns and arrangements of waveguide segments across adjacent dies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If photonic devices are used in integrated circuits for faster signal transmission, then signal transmission speed is improved, but the devices become sensitive to process variation and mask shifts which worsens manufacturing precision

Engineering Contradiction:
Improvesignal transmission speedVSAvoidwaveguide pattern precision
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by forming stitch patterns at specific locations before final lithography processing. These pre-positioned patterns serve as reference markers that enable detection and correction of mask shifts during subsequent manufacturing steps, thereby compensating for the sensitivity to process variation while maintaining high signal transmission speeds

Inventive Principle:
Principle #10Preliminary action

2Productivity

If optical signals propagate along waveguides across multiple dies, then signal transmission capability is improved, but stitch loss increases due to mask shifts and process variation

Engineering Contradiction:
Improvesignal transmission capabilityVSAvoidstitch loss
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent implements feedback by using the stitch patterns as reference markers to monitor mask alignment across die boundaries. The measured deviations from expected pattern positions provide feedback information that is used to correct mask shifts in real-time during lithography, thereby reducing stitch loss and maintaining signal transmission capability across multiple dies

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent applies parameter changes by adjusting mask alignment parameters based on the detected deviations in stitch pattern positions. By dynamically modifying the positioning parameters of subsequent lithography masks according to measured variations, the system compensates for process variation and minimizes stitch loss while maintaining optical signal transmission across die boundaries

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If stitch patterns are introduced to monitor and correct mask shifts, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvemask alignment precisionVSAvoidstitch structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by placing stitch patterns only at specific critical locations where die-to-die alignment is most challenging, rather than uniformly across the entire device. This localized approach provides the necessary manufacturing precision for mask alignment while minimizing the overall complexity increase by limiting the number of additional structures to only where they are most needed

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20250004201A1Semiconductor stitch structure and method for forming the same
Publication Date: 2025.01.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250004201A1 patent drawing
  • US20250004201A1 patent drawing
  • US20250004201A1 patent drawing

AI summary

A semiconductor structure includes a plurality of semiconductor dies, a first stitch structure disposed in the plurality of semiconductor dies, and a second stitch structure disposed in at least two adjacent semiconductor dies of the plurality of semiconductor dies. The semiconductor dies are arranged to form a column or a row. The first stitch structure crosses all interfaces between the semiconductor dies. The second stitch structure crosses an interface between the at least two adjacent semiconductor dies.