Stitched Chip Stitching Accuracy Verification

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Solution Overview

Problem

Conventional photolithography equipment has a limited field of exposure, restricting the size of chips that can be manufactured on a single wafer, and existing methods for verifying stitching accuracy are subjective and unreliable.

Innovation Solution

Inserting test structures within a reticle layout to evaluate stitching accuracy through electrical measurements, specifically using Kelvin (4-wire) resistance measurements at actual stitch boundaries of stitched chips on a wafer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If conventional photolithography equipment is used with limited field of exposure, then the equipment can be simpler and more cost-effective, but the chip size that can be manufactured on a single wafer is limited

Engineering Contradiction:
Improvechip sizeVSAvoidfield of exposure
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The reticle is divided into multiple fields that are exposed separately on different areas of the wafer. These fields are then stitched together to form a larger chip, allowing the manufacturing of chips larger than the field of exposure of conventional photolithography equipment.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If optical methods are used to verify stitching accuracy, then the verification process can be non-contact and quick, but the method becomes subjective and unreliable

Engineering Contradiction:
Improvestitching accuracyVSAvoidverification reliability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent replaces optical verification methods with electrical measurement methods. Test structures with known resistance values are formed at stitch boundaries, and electrical measurements are used to verify stitching accuracy, providing objective and reliable verification results.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Measurement precision

If test structures are inserted within the reticle layout, then stitching accuracy can be objectively verified through electrical measurements, but the reticle layout becomes more complex

Engineering Contradiction:
Improvestitching accuracy verificationVSAvoidreticle layout
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

Test structures with known resistance values are pre-formed at predetermined locations in the reticle layout before the actual chip fabrication. These test structures are positioned at stitch boundaries to enable subsequent electrical measurements that verify stitching accuracy.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Provides an objective and accurate method for verifying stitching accuracy, ensuring the quality and functionality of larger stitched chips by precisely determining resistance between test structures, thereby improving the manufacturing process.

Implementation Method 1

a field in a reticle is repeatedly exposed on different areas of a wafer until the entire photoresist layer has been exposed on the wafer

Methodology Applied
Scientific EffectPhotolithography: Photopolymerisation

Implementation Method 2

Electrical measurements are then performed on the test structures at actual stitch boundaries of the stitched chip to evaluate stitching accuracy

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS8803542B2Method and apparatus for verifying stitching accuracy of stitched chips on a wafer
Publication Date: 2014.08.12 BAE SYSTEMS INFORMATION ANDELECTRONIC SYSTEMS INTEGRATION INC
  • US8803542B2 patent drawing
  • US8803542B2 patent drawing
  • US8803542B2 patent drawing

AI summary

A method for verifying stitching accuracy of a stitched chip on a wafer is disclosed. Initially, a set of test structures are inserted within a reticle layout. An exposure program is executed to control a photolithography equipment having a stepper to perform multiple exposures of the reticle on a wafer to generate a stitched chip on the wafer. Electrical measurements are then performed on the test structures at actual stitch boundaries of the stitched chip to evaluate stitching accuracy of the stitched chip.