Stitched Die Microfluidic Cooling for Heat-Limited Scaling

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Solution Overview

Problem

The challenge of maintaining mobility improvement and short channel control in microelectronic devices as device dimensions scale below the 10 nanometer node, coupled with the constraints on lithographic processes in patterning semiconductor features, is exacerbated by the trade-off between critical dimension and spacing in multi-gate and nanowire transistors.

Innovation Solution

The implementation of stitched dies with integrated cooling structures, utilizing conductive interconnections and microfluidic channels, addresses these challenges by enabling efficient heat dissipation and reducing the need for package-level cooling solutions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If device dimensions are scaled down to increase integration density, then capacity and integration level are improved, but heat dissipation becomes more difficult and device performance deteriorates

Engineering Contradiction:

Improveintegration densityVSAvoidheat dissipation

Core Design Contradiction:

Quantity of substanceVSTemperature

Solution Approach 1:

The patent divides the semiconductor device into multiple stitched dies that are separately cooled by individual microfluidic channels. This segmentation allows each die to have dedicated cooling pathways, improving heat dissipation efficiency while maintaining high integration density through the stitched die architecture.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces microfluidic channels that extend vertically through the substrate, adding a third dimension to heat dissipation. This vertical cooling approach complements the horizontal scaling of device dimensions, enabling effective heat management in three-dimensional space while maintaining high integration density.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If multi-gate and nanowire transistors are used to improve short channel control, then device performance is improved, but lithographic process constraints increase due to trade-off between critical dimension and spacing

Engineering Contradiction:

Improveshort channel controlVSAvoidlithographic process constraints

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The patent replaces conventional planar lithographic patterning with self-aligned stitching approaches that use mechanical alignment features and conductive interconnections. This substitution reduces reliance on extreme lithographic precision while maintaining the benefits of multi-gate and nanowire transistor architectures for improved short channel control.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

3Temperature

If conventional cooling approaches are used at package level, then heat dissipation is achieved, but device miniaturization and performance optimization are limited

Engineering Contradiction:

Improveheat dissipationVSAvoiddevice miniaturization

Core Design Contradiction:

TemperatureVSLength of moving object

Solution Approach 1:

The patent incorporates cooling structures directly into the semiconductor substrate during the fabrication process, before packaging. This preliminary integration of microfluidic channels and cooling features enables effective heat dissipation at the device level, allowing for further miniaturization without being constrained by package-level cooling limitations.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances device performance and miniaturization by optimizing heat management and reducing the complexity of lithographic processes, thereby improving mobility and short channel control in advanced semiconductor architectures.

Implementation Method 1

microfluidic channels...addresses these challenges by enabling efficient heat dissipation

Methodology Applied

Scientific EffectConvection: Convection

Implementation Method 2

Heat spreader...coupled to the first side of the first and second dies

Methodology Applied

Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS12432897B2Cooling approaches for stitched dies

Publication Date: 2025.09.30 INTEL CORP

AI summary

Stitched dies having a cooling structure are described. For example, an integrated circuit structure includes a first die including a first device layer and a first plurality of metallization layers over the first device layer. The integrated circuit structure also includes a second die including a second device layer and a second plurality of metallization layers over the second device layer, the second die separated from the second die by a scribe region. A common conductive interconnection is coupling the first die and the second die at a first side of the first and second dies. A plurality of microfluidic channels is coupled to the first side of the first and second dies.