Shallow Trench Isolation Liner Stress Management

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Solution Overview

Problem

The increasing aspect ratio of shallow trench isolation (STI) structures in semiconductor manufacturing leads to voids in the isolation film, affecting isolation properties and subsequently reducing the performance of semiconductor devices, with existing high aspect ratio processes causing detrimental effects to both NMOS and PMOS transistors due to tensile stress.

Innovation Solution

A method involving the formation of nitrogen-doped silicon oxide liner layers between STI structures and the substrate to release tensile stress, combined with the use of different liner layers in different regions to optimize transistor performance, including a rapid thermal oxy-nitridation process to adjust stress levels and improve isolation quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the aspect ratio of STI structures is increased to accommodate smaller critical dimensions, then the isolation quality improves, but voids form inside the isolation film affecting isolation properties

Engineering Contradiction:
Improveisolation qualityVSAvoidisolation properties
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

A liner layer is introduced as an intermediary between the isolation film and the substrate. This liner layer serves as a stress buffer that prevents tensile stress from causing void formation in the isolation film, thereby maintaining both high aspect ratio benefits and isolation reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent applies rapid thermal oxy-nitridation to modify the physical and chemical parameters of the liner layer, transforming it from a simple barrier into a stress-managing component that can accommodate high aspect ratios without compromising isolation film integrity

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If HARP is used to form the isolation layer to match high aspect ratio requirements, then voids are reduced, but detrimental stress effects occur on subsequently formed semiconductor devices

Engineering Contradiction:
Improveaspect ratio matchingVSAvoidtensile stress effects
Core Design Contradiction:
Manufacturing precisionVSObject-generated harmful factors

Solution Approach 1:

The liner layer acts as a stress buffer between the HARP-formed isolation film and the substrate, absorbing and distributing tensile stress to prevent harmful effects on semiconductor devices while maintaining the high aspect ratio structure

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

Rapid thermal oxy-nitridation modifies the liner layer's mechanical properties, changing its stress characteristics from harmful tensile stress to a more benign state that protects underlying devices

Inventive Principle:
Principle #35Parameter changes

3Productivity

If the size of STI structures is reduced to increase integration level, then device density improves, but the aspect ratio increases making void formation more likely

Engineering Contradiction:
Improveintegration levelVSAvoidvoid formation risk
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The liner layer serves as a protective intermediary that enables the formation of high aspect ratio STI structures without void formation, thus allowing continued size reduction and integration level improvement

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The liner layer is formed preliminarily before depositing the isolation film, pre-establishing a stress-buffering structure that prevents void formation during subsequent isolation film formation in high aspect ratio trenches

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the performance of both NMOS and PMOS transistors by managing stress and reducing void formation, thereby improving the overall isolation and carrier mobility in semiconductor devices.

Implementation Method 1

performing a rapid thermal oxy-nitridation process on the first liner layer to release a tensile stress between the first liner layer and the substrate

Methodology Applied
Scientific EffectRapid thermal oxy-nitridation: Heat Treatment

Data Source

PatentUS9559017B2Method of forming shallow trench isolations for a semiconductor device
Publication Date: 2017.01.31 SEMICON MFG INT (SHANGHAI) CORP
  • US9559017B2 patent drawing
  • US9559017B2 patent drawing
  • US9559017B2 patent drawing

AI summary

A method for forming a semiconductor structure is provided. The method includes providing a substrate having a first region and a second region; and forming at least one first trench in the first region of the substrate, and at least one second trench in second region of the substrate. The method also includes forming a first liner layer on side and bottom surfaces of the first trench, and the side and bottom surfaces of the second trench; and performing a rapid thermal oxy-nitridation process on the first liner layer to release a tensile stress between the first liner layer and the substrate. Further, the method includes removing a portion of the first liner layer in the first region to expose the first trench; and forming a second liner layer on the side and bottom surface of the first trench.