High Young's Modulus Liner for Shallow Trench Isolation Stress Management
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Solution Overview
Problem
Current shallow trench isolation structures in semiconductor technology do not effectively enhance the stress-induced performance improvements in transistor channels, as they suffer from stress relaxation issues that reduce the effectiveness of embedded stressor regions.
Innovation Solution
A semiconductor structure with a high Young's modulus liner is introduced in the shallow trench isolation region, deposited on the interior surface and adjacent to the source-drain regions of field effect transistors, to prevent stress relaxation and maintain the desired stress levels, thereby enhancing carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional shallow trench isolation structure is used, then the device scaling and fabrication simplicity are maintained, but the stress relaxation occurs in the transistor channel reducing carrier mobility
Solution Approach 1:
The shallow trench isolation structure is segmented into multiple functional layers: a first fill oxide layer for stress application, a high Young's modulus liner layer for stress confinement, and a second fill oxide layer for stress maintenance. This segmentation allows each layer to perform its specific function optimally, preventing stress relaxation while maintaining device scaling
Solution Approach 2:
The isolation structure uses composite materials with different mechanical properties - combining oxide materials (for stress generation) with a high Young's modulus liner material (for stress confinement). This composite structure creates the desired stress profile in the transistor channel without excessive structural complexity
2Reliability
If the trench isolation region is made deeper to improve stress confinement, then stress relaxation is reduced, but deposition challenges and manufacturing difficulty increase
Solution Approach 1:
The patent changes the depth parameter of the trench isolation region to an optimized shallow depth, and compensates for stress confinement by adjusting the Young's modulus parameter of the liner material. This parameter change approach achieves effective stress confinement without the manufacturing difficulties associated with deep trench deposition
Solution Approach 2:
The high Young's modulus liner is applied locally at the interface between the fill oxide and the transistor channel, precisely where stress confinement is needed. This localized application of enhanced mechanical properties achieves effective stress management without requiring complex deep trench structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The high Young's modulus liner increases carrier mobility by maintaining stress levels, improving the performance of both n-channel and p-channel MOS transistors, and simplifies processing by avoiding deposition challenges associated with deep trench isolation.
Implementation Method 1
A semiconductor structure with a high Young's modulus liner is introduced in the shallow trench isolation region, deposited on the interior surface and adjacent to the source-drain regions of field effect transistors, to prevent stress relaxation and maintain the desired stress levels
Data Source
AI summary
A semiconductor structure with an improved shallow trench isolation (STI) region and method of fabrication is disclosed. The STI region comprises a lower portion filled with oxide and an upper portion comprising a high Young's modulus (HYM) liner disposed on the lower portion and trench sidewalls and filled with oxide. The HYM liner is disposed adjacent to source-drain regions, and serves to reduce stress relaxation within the shallow trench isolation (STI) oxide, which has a relatively low Young's modulus and is soft. Hence, the HYM liner serves to increase the desired stress imparted by the embedded stressor source-drain regions, which enhances carrier mobility, thus increasing semiconductor performance.