System Trace Module Power Event Visibility
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Solution Overview
Problem
Complex system-on-a-chip (SoC) designs pose challenges in power management due to increasing integration and rising power consumption, as existing test and debug standards like IEEE 1149.1 do not effectively provide visibility into power management events, making it difficult to optimize and debug power-related issues.
Innovation Solution
The System Trace Module (STM) within the MIPI Debug and Trace Interface is utilized to encapsulate power management events into System Trace Protocol (STP) messages, allowing for real-time monitoring and analysis of power state changes across voltage, power, and clock domains, enabling efficient power management optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If IEEE 1149.1 (JTAG) standard is used for test and debug, then test and debug functionality is provided, but visibility into power management events is insufficient
Solution Approach 1:
The patent segments the tracing functionality by introducing a dedicated System Trace Module (STM) that operates independently from the JTAG interface. The STM captures power management events separately through dedicated trace ports, allowing simultaneous software debugging and hardware power event monitoring without interference between the two functions.
Solution Approach 2:
The patent introduces an intermediary component - the System Trace Module with its own trace protocol and capture logic - that sits between the power management hardware and the external debugging equipment. This intermediary captures and transports power management trace data independently, providing the missing visibility without requiring modification of the existing JTAG standard.
2Adaptability or versatility
If chip integration is increased, then functionality is improved, but power consumption increases and power management becomes more complex
Solution Approach 1:
The patent implements autonomous power management controllers that automatically adjust voltage and clock frequency based on real-time monitoring of functional unit activity. The system monitors its own power consumption patterns and self-adjusts operating parameters without external intervention, optimizing power efficiency as integration and functionality increase.
Solution Approach 2:
The patent establishes a feedback loop where power management events are traced and monitored in real-time, providing visibility into the relationship between functional unit activity and power consumption. This feedback enables dynamic adjustment of power management strategies to optimize energy efficiency while maintaining required functionality.
3Loss of information
If power management events are monitored in real-time, then visibility and optimization capability are improved, but additional tracing infrastructure is required
Solution Approach 1:
The patent designs the System Trace Module to serve multiple functions: it captures both software debugging information and hardware power management events through a unified trace infrastructure. The STM can simultaneously trace multiple types of events using the same port and protocol mechanism, reducing the need for separate dedicated infrastructure for each tracing purpose.
Data Source
AI summary
In a method for monitoring power consumption by a system within an integrated circuit, one or more software programs are executed on the system on a chip (SOC). While the program executes, power control settings of a plurality of functional units within the SOC may be adjusted in response to executing the one or more software programs, whereby power consumption within the SOC varies over time. The power control settings may be changed in response to explicit directions from the executing software, or may occur autonomously in response to load monitoring control modules within the SOC. A sequence of power states is reported for the plurality of functional units within the SOC. Each of the sequence of power states may include clock frequencies from multiple clock domains, voltage levels for multiple voltage domains, initiator activity, target activity, memory module power enablement, or power enablement of each of the plurality of functional units.