Shallow Trench Isolation Stress Memorization for Semiconductor Devices
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Solution Overview
Problem
Existing methods for introducing stress into semiconductor channel regions are complex and costly, requiring additional processing steps and materials to enhance carrier mobility, such as epitaxial growth and trench formation.
Innovation Solution
A method involving the formation of shallow trench isolations with high stress materials like silicon oxide, silicon nitride, or diamond-like amorphous carbon, where the stress is memorized by the gate and enhanced by backfilling the trench with a high-stress material, simplifying the process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epitaxial growth and trench formation are used to introduce stress into the channel region, then carrier mobility is enhanced, but the manufacturing process becomes complicated and costly
Solution Approach 1:
The patent changes the material parameter of the shallow trench isolation from conventional low-stress materials to high-stress materials (such as silicon nitride or diamond-like carbon) that can generate significant stress in the channel region. This parameter change enables stress introduction without requiring complex epitaxial growth processes, thereby enhancing carrier mobility while simplifying the manufacturing process
Solution Approach 2:
The patent extracts the stress-generation function from the complex epitaxial growth process and transfers it to the shallow trench isolation structure itself. By using high-stress materials in the STI, the stress is naturally applied to the channel region during standard fabrication processes, eliminating the need for separate stress-introduction steps
2Reliability
If different crystal orientations are used for NMOS and PMOS active regions, then carrier mobility is improved, but extra processing steps are required which prolong process time and increase cost
Solution Approach 1:
The patent makes the shallow trench isolation structure universally applicable to both NMOS and PMOS devices by using high-stress materials that can provide the necessary stress for both device types. This universal approach eliminates the need for separate epitaxial growth processes for different device types, reducing process time and complexity while maintaining improved carrier mobility for both NMOS and PMOS
3Reliability
If SiGe and SiC source and drain regions are used to apply stress, then carrier mobility is enhanced, but additional etching and epitaxial growth steps are required which increase cost
Solution Approach 1:
The patent uses conventional silicon-based shallow trench isolation materials (silicon oxide, silicon nitride, or diamond-like carbon) that are inexpensive and already part of the standard fabrication process, replacing the expensive SiGe and SiC epitaxial growth. These materials provide sufficient stress generation without requiring additional costly epitaxial steps, making the process more economically viable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach efficiently and inexpensively increases carrier mobility in the channel region, improving device performance by applying stress through the shallow trench isolation, thereby simplifying the manufacturing process and reducing costs.
Implementation Method 1
a method for introducing a stress into a channel region... by introducing a stress into the channel region using a technology, so that the driving capability of the device can be enhanced
Data Source
AI summary
The present invention discloses a method for manufacturing a semiconductor device, comprising: forming a first shallow trench isolation in a substrate; forming a semiconductor device structure in an active region surrounded by the first shallow trench isolation; removing the first shallow trench isolation and leaving a shallow trench in the substrate; and filling the shallow trench with an insulating material to form a second shallow trench isolation. In the method for manufacturing the semiconductor device according to the present invention, after forming the shallow trench isolation with high stress, the high stress is memorized by the gate to enhance the stress in the channel region by etching, removing, and then backfilling the shallow trench isolation, so that the carrier mobility in the channel regions to be formed later can be increased and the device performance can be improved.