ST-MRAM Self-Reference Read Method for Peak Current Reduction
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Solution Overview
Problem
Spin-torque magnetoresistive memory (ST-MRAM) faces challenges with high peak write current and longer write pulse durations during short WRITE operations, limiting scalability and non-volatility, especially during the PRECHARGE operation in memory arrays.
Innovation Solution
A method involving destructive read with immediate write-back in ST-MRAM, using reset and set write current pulses based on majority bit detection and inversion, minimizing write-back pulses and enabling efficient data transfer during ACTIVATE operations, with error correcting code (ECC) organization and separate write clock phase generators for independent execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spin-torque switching is used in ST-MRAM, then non-volatility and fast write speeds are achieved, but high peak write current and long write pulse durations limit scalability
Solution Approach 1:
The patent segments the write operation into two distinct phases: a first write operation that writes data to a first location, and a second write operation that writes data to a second location. These operations are executed at different times with different current requirements, allowing the system to manage peak current by avoiding simultaneous high-current operations while maintaining non-volatile storage benefits.
Solution Approach 2:
The patent performs preliminary data transfer to a first location during the first write operation, then uses this pre-positioned data during the second write operation. This preliminary action allows the system to prepare data in advance when current requirements are lower, avoiding the need to simultaneously manage high current pulses for multiple write operations.
2Speed
If write current pulse duration is reduced to improve write speed, then fast write speeds are achieved, but switching current requirements increase
Solution Approach 1:
The patent performs preliminary data transfer to a first location during the first write operation with optimized pulse duration, then uses this pre-positioned data during the second write operation. This preliminary action allows the system to prepare data in advance when current requirements are lower, avoiding the need to simultaneously manage high current pulses for multiple write operations.
Solution Approach 2:
The patent dynamically adjusts the timing and current parameters of write operations based on the operational phase. The first write operation uses different current pulse characteristics than the second write operation, allowing optimization of write speed in one phase while managing current requirements in another phase, rather than using fixed parameters throughout.
3Reliability
If destructive read with immediate write-back is used, then data non-volatility is ensured, but additional write pulses increase peak current
Solution Approach 1:
The patent segments the write operation into two distinct phases: a first write operation that writes data to a first location, and a second write operation that writes data to a second location. These operations are executed at different times with different current requirements, allowing the system to manage peak current by avoiding simultaneous high-current operations while maintaining non-volatile storage benefits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces peak write current, shortens write pulse durations, and ensures non-volatility by minimizing write-back pulses and optimizing data transfer efficiency, enhancing the scalability and performance of ST-MRAM.
Implementation Method 1
The angular momentum carried by the spin-polarized tunneling current causes reversal of the free layer
Implementation Method 2
exhibits an electrical resistance that depends on the magnetic state of the device
Data Source
Figure 1~4
Figure 3
Figure 5
AI summary
A spin-torque magnetoresistive memory comprises an array (602) of spin-torque magnetoresistive memory bits; a plurality of latches (626); array read circuits (610) coupled to the array of bits (602) and the plurality of latches (626), wherein the array read circuits are configured to: sample bits in a page within the array of bits, wherein sampling provides a sampled voltage for each of the bits in the page, wherein the array read circuits are configured to sample each bit in the page by applying a first voltage across the bit and converting a current resulting from applying the first voltage to the sampled voltage; after sampling the bits in the page, apply a first write current pulse to each of the bits in the page to set all of the bits in the page to a first logic state; after applying the first write current pulse to each of the bits in the page, resample each of the bits in the page to provide a resampled voltage for each bit in the page, wherein the array read circuits are configured to resample each bit by reapplying the first voltage across the bit and adding an offset current to a current resulting from reapplying the first voltage across the bit, wherein the array read circuits are configured to generate the resampled voltage for each bit using the offset current and the current resulting from reapplying the first voltage across the bit; for each bit in the page, compare the resampled voltage with the sampled voltage to determine a bit state for the bit, wherein the bit state for each bit is either the first logic state or a second logic state; and store the bit state for each bit in the page in a corresponding latch of the plurality of latches (626). The memory comprises further array write circuits (612) coupled to the array of bits (602) and the plurality of latches (626), the array write circuits (612) configured to, for each of the bits in the page having the second logic state as stored in the plurality of latches (626), initiate a write-back to reset the bit to the second state in the array, wherein the write-back for each bit includes applying a second write current pulse to set the bit to the second state.