Stochastic ADC Architecture for Low-Noise, Low-Power Conversion
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Solution Overview
Problem
Conventional analog-to-digital converters (ADCs) face challenges in reducing comparator noise, which degrades signal-to-noise ratio (SNR) and Effective Number of Bits (ENOB), and increasing power consumption when trying to minimize decision errors, as it is wasteful to use high-power comparators for all comparisons, especially when only one is noise-critical.
Innovation Solution
The proposed ADC circuit employs a two-stage architecture where the first stage generates a digital representation and a residue signal, and the second stage performs stochastic conversion using a plurality of comparators activated by a clock signal, allowing the system to estimate both the sign and magnitude of the input signal by combining the results from both stages, thereby reducing power consumption by using only the power-critical comparison.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the probability of comparator wrong decision is decreased by using higher power consumption, then measurement precision is improved, but use of energy increases
Solution Approach 1:
The patent applies local quality by differentiating between critical and non-critical comparisons. Only the most significant comparison (where the input signal is closest to the threshold) uses a high-power, low-noise comparator, while all other comparisons use low-power comparators. This selective allocation of resources based on local needs resolves the contradiction by providing high accuracy only where it is truly necessary.
Solution Approach 2:
The patent segments the comparison process into multiple stages: first identifying the critical comparison point, then applying high-precision comparison only at that specific point. The ADC architecture divides the conversion process into coarse quantization (using low-power comparators) and fine quantization (using high-power comparator only when needed), thereby resolving the power-accuracy tradeoff.
2Measurement precision
If comparator noise is reduced to improve signal-to-noise ratio, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent reduces device complexity by applying low-noise comparison only locally at the critical decision point rather than throughout the entire ADC. The architecture uses simple low-power comparators for most comparisons and reserves complex high-precision comparator resources only for the most significant bit decision, thereby maintaining high SNR without requiring complex architecture throughout.
Solution Approach 2:
The ADC is segmented into multiple conversion stages with different precision requirements. The patent separates the conversion process into coarse quantization (handling most bits with simple comparators) and fine quantization (handling the most significant bit with a high-precision comparator), thus achieving high measurement precision without requiring the entire device to be complex.
3Measurement precision
If all comparisons use high-power low-noise comparators to ensure accuracy, then measurement precision is improved, but use of energy increases
Solution Approach 1:
The patent implements local quality by identifying which specific comparison is most critical to conversion accuracy and allocating high-power comparator resources only to that specific comparison. All other comparisons use minimal power, achieving near-optimal accuracy with significantly reduced total power consumption compared to using high-power comparators for all comparisons.
Solution Approach 2:
The conversion process is segmented into multiple stages with differentiated power requirements. The patent uses low-power comparators for the majority of comparison operations and reserves high-power comparator operation only for the most significant bit determination, thereby segmenting power consumption according to actual accuracy needs at each stage.
Data Source
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AI summary
The present invention is related to an analog-to-digital (A/D) converter circuit arranged for receiving an analog input signal (1) and for outputting a digital representation (6) of said analog input signal (1). The A/D converter circuit comprises: - a first converter stage (2) configured for receiving the analog input signal (1) and for generating a first set (3) of conversion bits, a first completion signal (7) and a residual analog output signal (4) representing the difference between the analog input signal and a signal represented by said first set of conversion bits, - a second converter stage (5) comprising o a clock generation circuit (8) arranged for receiving the first completion signal and for generating a clock signal, o a plurality of comparators each being configured for receiving the residual analog output signal and a common reference voltage, said plurality of comparators arranged for being activated by the clock signal and for outputting a plurality of comparator decisions, o a digital processing stage (9) configured for receiving the plurality of comparator decisions and for generating a second set of conversion bits, - means for generating the digital representation of the analog input signal by combining the first and second set of conversion bits.