Stochastic Computing Circuit Pulse Duty Cycle Control

The patent changes the fundamental parameter representation from binary digits to pulse duty cycles. Instead of using binary bits that can flip between 0 and 1, the system uses pulses with varying duty cycles (ratio of high to total period) to represent computational values. This parameter transformation makes the system inherently more robust because duty cycle variations are continuous and less sensitive to single-bit errors, directly resolving the accuracy and reliability contradiction.

The patent substitutes the traditional binary digital logic system with a pulse-based stochastic computing system. Rather than relying on binary state transitions and logical gates, the invention uses pulse generation, modulation, and statistical analysis to perform computations. This substitution replaces the fragile binary state machine with a more robust pulse-based system where information is encoded in temporal characteristics rather than discrete states, improving reliability while maintaining computational capability.

The patent implements self-service by enabling the computing circuit to perform operations directly on pulse streams without requiring data to be loaded from and stored back to memory. The stochastic computing circuit processes information in-place using pulse-based operations, eliminating the memory bottleneck. This self-service approach allows the computing system to operate independently of memory bandwidth constraints, directly improving productivity while reducing dependency on memory quantity.

The patent employs periodic pulse sequences with specific duty cycles to represent and process computational data. Instead of using continuous data streams that require memory buffering, the system uses periodic pulse patterns that can be processed in real-time as they arrive. This periodic action enables streaming computation where data flows continuously through the circuit without requiring large memory bandwidth for data transfer, thereby improving computing efficiency independent of memory capacity.

The patent converts the harmful effect of bit errors into a beneficial feature by using statistical pulse analysis. Instead of treating individual pulse variations as errors to be corrected, the system accumulates many pulses and uses statistical measures (mean, variance) to extract the computational result. This approach transforms what would be harmful noise in binary systems into useful statistical information, improving accuracy while making the system naturally resilient to individual pulse errors.

The patent performs preliminary statistical analysis by accumulating multiple pulses before extracting the final computational result. Rather than processing single data points that are vulnerable to errors, the system pre-processes data by collecting ensembles of pulses and computing statistical characteristics. This preliminary action of data accumulation and statistical preprocessing filters out random errors before the final computation, significantly improving result accuracy while maintaining robustness against bit errors.