Stochastic Equality Nodes With Edge Memory Against Decoder Latching
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Solution Overview
Problem
Existing methods for decoding Low Density Parity Check (LDPC) and Reed-Solomon (RS) codes are complex and costly due to their sensitivity to switching activity and the complexity of hardware implementations, particularly in stochastic decoding processes where 'latching' issues and high-density parity check matrices hinder efficient error correction.
Innovation Solution
A stochastic decoding method using logic circuitry with counter circuitries and memory elements to manage equality and parity check nodes, which represent a factor graph of a linear code, allowing for scalable and efficient decoding by incrementing or decrementing counters based on node states and using edge memories to re-randomize stochastic streams, thereby preventing latching and improving convergence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If stochastic decoding is used to reduce hardware complexity, then device complexity is reduced, but latching issues occur that prevent proper decoding operation
Solution Approach 1:
A switching activity control circuit is introduced as an intermediary component between the stochastic decoding logic and the equality nodes. This circuit monitors and controls the switching activity levels, preventing latching by ensuring minimum transition thresholds are met, thereby enabling reliable decoding operation while maintaining stochastic computation's hardware simplicity
Solution Approach 2:
The patent dynamically adjusts the switching activity parameter in the stochastic decoding process. By modifying the switching activity control signal based on detected latching conditions, the system changes the operational parameters of equality nodes to prevent correlation between incoming stochastic messages, thus resolving the latching problem while maintaining low hardware complexity
2Device complexity
If equality nodes process stochastic messages to reduce complexity, then device complexity is reduced, but correlation between messages causes latching that stops bit transitions
Solution Approach 1:
The patent implements a feedback mechanism where the switching activity control circuit continuously monitors the operational state of equality nodes and adjusts the switching activity control signal accordingly. When latching is detected (indicated by lack of bit transitions), the feedback loop increases switching activity to break the correlation, ensuring continuous proper operation while maintaining the simplified stochastic hardware architecture
Data Source
AI summary
The present invention relates to a decoding method and system for stochastic decoding of linear block codes with parity check matrix. Each encoded sample of a set of encoded samples is converted into a corresponding probability. For each probability a corresponding probability message is the generated by encoding each probability as a sequence of digital symbols. Each probability message is then provided to a respective node of a logic circuitry for stochastic decoding. The logic circuitry represents a factor graph of the parity check matrix of the linear block code. Using the logic circuitry each probability message is processed for determining an estimated sequence of information symbols. If an equality node is in a hold state a chosen symbol is provided from a corresponding memory which is updated by storing output symbols from the equality node when the same is in a state other than a hold state.