Stochastic Microprocessor Parallel Computing Energy

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Solution Overview

Problem

Traditional microprocessors have reached physical limits in computing speed and miniaturization, leading to high energy consumption and costly infrastructure requirements for probabilistic and stochastic computations, which are essential in fields like finance, weather forecasting, and cryptography.

Innovation Solution

A stochastic microprocessor with elementary modules that receive random binary input signals, generate output signals based on logic functions, and utilize stochastic clocks for memory control, allowing for parallel computations and reducing energy consumption by abandoning deterministic operation constraints.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Power

If traditional microprocessors operate in parallel to exceed computing speed limits, then computing power increases, but energy consumption and infrastructure costs increase significantly

Engineering Contradiction:
Improvecomputing powerVSAvoidenergy consumption
Core Design Contradiction:
PowerVSUse of energy by moving object

Solution Approach 1:

The patent replaces deterministic mechanical clock synchronization with stochastic timing mechanisms. Each processing element operates with independent random timing, eliminating the need for centralized clock distribution and synchronization infrastructure, thereby reducing energy consumption while maintaining parallel computing power

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The invention changes the fundamental operating parameter from deterministic to stochastic behavior. By allowing processing elements to operate with random timing rather than synchronized clocks, the system achieves parallel computing without the energy overhead of traditional synchronization mechanisms

Inventive Principle:
Principle #35Parameter changes

2Length of moving object

If transistor size is reduced below 10 nm for further miniaturization, then device density increases, but circuit behavior becomes unstable and non-deterministic

Engineering Contradiction:
Improvetransistor sizeVSAvoidcircuit stability
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The patent converts the harmful non-deterministic behavior of sub-10nm transistors into a beneficial feature. By embracing stochastic operation modes, the system exploits the inherent randomness at nanoscale to enable new computing paradigms that are naturally suited for probabilistic algorithms and machine learning workloads

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

Instead of trying to eliminate randomness to maintain determinism, the invention inverts the approach by deliberately introducing and utilizing stochastic behavior. This allows the system to operate reliably in the non-deterministic regime where traditional deterministic circuits would fail

Inventive Principle:
Principle #13The other way round (Inversion)

3Reliability

If deterministic operation is maintained for reliability, then system stability is ensured, but thermal noise limits are reached and further miniaturization becomes impossible

Engineering Contradiction:
Improvesystem stabilityVSAvoidthermal noise threshold
Core Design Contradiction:
ReliabilityVSTemperature

Solution Approach 1:

The patent inverts the traditional approach by abandoning determinism in favor of stochastic operation. This allows the system to operate below the thermal noise threshold where deterministic circuits become unreliable, converting thermal noise from a limiting factor into an operational regime for nanoscale devices

Inventive Principle:
Principle #13The other way round (Inversion)

Data Source

PatentUS10437561B2Stochastic parallel microprocessor
Publication Date: 2019.10.08 CENT NAT DE LA RECH SCI (C N R S)
  • US10437561B2 patent drawing
  • US10437561B2 patent drawing

AI summary

The invention relates to a stochastic-type microprocessor.In some embodiments, the microprocessor comprises an elementary stochastic computation module able to receive, as input, two random and independent binary input signals each representing a binary coding of two respective given input probability values, and able to generate, as output, a random binary output signal.The elementary module comprises:a programmable logic unit, able to combine two input signals to generate an output signal;an addressable memory, able to store an output probability value coded by an output signal generated by the logic unit;a first stochastic clock, able to produce a first clock signal;a second stochastic clock, able to produce a second clock signal.