Stochastic Time-to-Digital Converter for Linear Phase Measurement

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Solution Overview

Problem

Designing a time-to-digital converter (TDC) with ultrafine resolution and linearity is challenging due to component mismatches in semiconductor processes, which can lead to non-linearity issues in stochastic TDCs.

Innovation Solution

A stochastic TDC is implemented with multiple arbiter cells that compare signal timings using selection signals to minimize integral non-linearity errors, utilizing different time offsets based on voltage selection and process corner characteristics, allowing for fine phase difference measurement without increasing component size or power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If component size is decreased to increase signal speed, then signal processing capability is improved, but component mismatch increases causing non-linearity in TDC

Engineering Contradiction:
Improvesignal speedVSAvoidcomponent matching
Core Design Contradiction:
SpeedVSManufacturing precision

Solution Approach 1:

The patent applies parameter changes by utilizing voltage selection to dynamically adjust the operating parameters of arbiter cells. By switching between different voltage levels (first voltage or second voltage), the time offset characteristics of each arbiter cell can be changed, allowing the system to compensate for component mismatches and improve linearity without changing the physical component size.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If stochastic TDC is used to achieve ultrafine resolution, then measurement precision is improved, but linearity deteriorates due to random component mismatch

Engineering Contradiction:
Improvephase difference resolutionVSAvoidlinearity
Core Design Contradiction:
Measurement precisionVSStability of the object's composition

Solution Approach 1:

The patent implements dynamics by making the arbiter cell characteristics adjustable through voltage selection. Instead of fixed component characteristics, the system dynamically selects operating voltages for each arbiter cell to create desirable time offset distributions. This dynamic adjustment allows the system to maintain both ultrafine resolution and improved linearity by adapting to process variations.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent employs feedback mechanisms through the selection signal generation process. The selection signals are determined based on process corner characteristics, implying a feedback loop that adjusts the operating parameters of arbiter cells according to measured or predicted performance. This feedback allows the system to compensate for random mismatches and maintain linearity while achieving ultrafine resolution.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If multiple arbiter cells with different thresholds are used, then ultrafine resolution is achieved, but device complexity increases

Engineering Contradiction:
Improveultrafine resolutionVSAvoidarbiter cell configuration
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies universality by designing arbiter cells that can operate in multiple modes through voltage selection. Each arbiter cell can function with different time offset characteristics depending on the applied voltage, allowing a single cell design to serve multiple purposes. This multi-functionality reduces the need for completely different cell designs and simplifies the overall system while maintaining ultrafine resolution capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP3657270B1Stochastic time-to-digital converter and operating method thereof
Publication Date: 2022.07.20 KOREA UNIV RES & BUSINESS FOUND
  • EP3657270B1 patent drawingFigure 1
  • EP3657270B1 patent drawingFigure 2~3
  • EP3657270B1 patent drawingFigure 4

AI summary

Disclosed is a stochastic time-to-digital converter, which includes a first arbiter cell that compares a timing of a reference signal and a timing of an input signal based on a voltage selected by a first selection signal from among a first voltage or a second voltage and outputs a first comparison result, a second arbiter cell that compares the timing of the reference signal with the timing of the input signal based on a voltage selected by a second selection signal from among the first voltage or the second voltage and outputs a second comparison result, and a binary converter that calculates a phase difference between the reference signal and the input signal based on the first comparison result and the second comparison result.