Stopper Layer Layout for Bit Line Contact Misalignment
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Solution Overview
Problem
Existing semiconductor devices face challenges in ensuring reliable contact between bit line contact plugs and cell channel structures, particularly when misalignment occurs during manufacturing processes.
Innovation Solution
The semiconductor device incorporates a stopper layer with a first insulating material and an upper mold layer with a second insulating material having etch selectivity, along with a cell channel structure and bit line contact plugs, to ensure accurate alignment and prevent short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional manufacturing processes are used without additional protective structures, then the device structure remains simple, but misalignment occurs between bit line contact plugs and cell channel structures leading to short circuits
Solution Approach 1:
The stopper layer acts as an intermediary structure between the upper mold layer and the cell channel structure. It provides a reference surface for alignment during manufacturing and prevents direct contact between misaligned bit line contact plugs and the cell channel structure, thereby eliminating short circuits without requiring complex alignment systems
Solution Approach 2:
The stopper layer is formed in advance before bit line contact plug deposition. It creates a protective barrier that cushions against misalignment errors, ensuring that even if contact plugs are misplaced, they will not directly short-circuit the cell channel structure. This preliminary protective measure prevents potential failures before they occur
2Reliability
If the stopper layer inner side surface is aligned with the upper stack inner side surface, then the structure is compact, but misalignment causes short circuits between contact plugs and cell channel structures
Solution Approach 1:
The stopper layer is deliberately designed with asymmetric positioning relative to the upper stack. The inner side surface of the stopper layer is offset from the inner side surface of the upper stack, creating an intentional asymmetric structure. This offset provides a safety margin that prevents short circuits while maintaining reasonable device compactness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the reliability of the semiconductor device by preventing short circuits even in cases of misalignment during manufacturing, thereby improving the overall performance and durability of the device.
Implementation Method 1
an upper mold layer on the stopper layer, the upper mold layer including a second insulating material having etch selectivity with respect to the stopper layer
Data Source
AI summary
A semiconductor device including a peripheral circuit layer on a substrate; a lower stack and upper stack on the substrate; a stopper layer on the upper stack and including an insulating material; an upper mold layer on the stopper layer; a cell channel structure extending through the layers, a side surface of the cell channel structure contacting the stopper layer; first and second capping layers; a word line separation structure including a protrusion protruding toward the stopper layer; and a bit line contact plug connected to the cell channel structure, wherein an inner side surface of the stopper layer is offset from an inner side surface of the upper stack, and in contact with the word line separation structure.