Storage Device With In-Storage Acceleration for Host Load Reduction

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Solution Overview

Problem

Existing storage devices struggle with inefficient computation offloading to hardware accelerators, particularly in large-capacity storage devices like SSDs, leading to suboptimal performance and efficiency.

Innovation Solution

Incorporating a controller, non-volatile memory, buffer memory, and an accelerator within the storage device, where the accelerator performs computations using a memory access module and computing module to process datasets directly from the buffer memory, reducing the need for host intervention.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If computation tasks are offloaded to hardware accelerators in storage devices, then processing speed and efficiency are improved, but device complexity increases

Engineering Contradiction:
Improvecomputation speedVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent combines the accelerator, buffer memory, and non-volatile memory into a single integrated storage device unit. The accelerator is directly coupled to the buffer memory and non-volatile memory within the same device, enabling computations to be performed locally without requiring external host system intervention. This merging approach allows computation offloading to improve processing speed while containing the complexity within a single integrated device rather than requiring complex inter-system connections.

Inventive Principle:
Principle #5Merging (Combining)

2Productivity

If the accelerator processes datasets directly from non-volatile memory, then computational load on host is reduced, but data access time increases due to memory hierarchy

Engineering Contradiction:
Improvecomputational load reductionVSAvoiddata access time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent implements a buffer memory that pre-loads and caches datasets from the non-volatile memory before the accelerator needs to process them. The buffer memory acts as an intermediate storage that prepares data in advance, so when the accelerator requires datasets for computation, the data is already available in the faster buffer memory rather than requiring direct access to the slower non-volatile memory. This preliminary action reduces data access time while still allowing the accelerator to independently process datasets and reduce host computational load.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12443368B2Storage device and memory system
Publication Date: 2025.10.14 SAMSUNG ELECTRONICS CO LTD
  • US12443368B2 patent drawing
  • US12443368B2 patent drawing
  • US12443368B2 patent drawing

AI summary

A storage device is provided. The storage device includes a controller which receives a command from a host for instructing performance of a first computation, a non-volatile memory which stores a plurality of datasets, a buffer memory to which a first dataset among the plurality of datasets stored in the non-volatile memory is provided in response to the command, and an accelerator which performs the first computation corresponding to the command, using the first dataset provided to the buffer memory. The accelerator includes a memory access module which receives a first input query for instructing the first computation and the first dataset from the buffer memory, and a first computing module which is connected to the memory access module and determines first final candidate data corresponding to the first input query, using the first dataset.