Storage Accelerator Memory Layout for Decompression Bandwidth Bottlenecks
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Solution Overview
Problem
Existing storage devices with increased data compression units face performance bottlenecks due to memory bandwidth limitations, particularly in CPU memory bandwidth growth lagging behind storage medium transfer bandwidth, hindering data read performance.
Innovation Solution
Implementing a storage device with a separate accelerator memory and a field programmable gate array (FPGA) or application-specific integrated circuit (ASIC) to handle data compression and decompression tasks, offloading these processes from the CPU, and using a programmable DRAM interface to manage data transfer efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of substance
If the data compression unit is increased to improve data reduction rate, then the data reduction rate is improved, but the memory bandwidth consumption increases and becomes a bottleneck
Solution Approach 1:
The patent divides the storage system into two independent memory segments: a first memory (DRAM) connected to the CPU and a second memory (buffer memory) connected to the storage medium. This segmentation allows the CPU to access only the necessary extracted data in the first memory while the second memory handles the large-volume compressed data, thereby reducing the memory bandwidth consumption of the CPU and resolving the bottleneck caused by increased compression units.
2Loss of substance
If data compression and decompression are executed by CPU to reduce data storage cost, then the data storage cost is reduced, but the CPU performance deteriorates
Solution Approach 1:
The patent extracts the decompression function from the CPU and assigns it to a dedicated storage device equipped with a decompression unit. This extraction allows the CPU to focus on higher-level tasks while the storage device handles the computationally intensive decompression process, thereby maintaining CPU performance while still achieving data reduction cost benefits.
Solution Approach 2:
The patent introduces a buffer memory (second memory) as an intermediary between the storage medium and the CPU. This buffer memory serves as a mediator that temporarily stores decompressed data, allowing the CPU to access only the specific data it needs without being burdened by the entire compressed data set, thus resolving both the performance and cost efficiency issues.
3Productivity
If the compression unit is increased to 64 kB to improve compression efficiency, then the compression efficiency is improved, but the amount of data to be read and written from memory becomes extremely larger
Solution Approach 1:
The patent segments the memory system into a first memory for CPU access and a second memory for storage medium access. This segmentation allows the system to maintain large compression units (64 kB) in the second memory without proportionally increasing the data transfer burden on the CPU, as the CPU only needs to access the extracted portion of data in the first memory.
Solution Approach 2:
The buffer memory acts as an intermediary that absorbs the large data volumes associated with increased compression units. By storing the entire 64 kB compressed data blocks in the buffer memory, the system can maintain high compression efficiency while the CPU interacts only with the smaller extracted data portions, thus resolving the contradiction between compression efficiency and data transfer volume.
Data Source
AI summary
The storage device includes a first memory, a process device that stores data in the first memory and reads the data from the first memory, and an accelerator that includes a second memory different from the first memory. The accelerator stores compressed data stored in one or more storage drives storing data, in the second memory, decompresses the compressed data stored in the second memory to generate plaintext data, extracts data designated in the process device from the plaintext data, and transmits the extracted designated data to the first memory.