Storage Adapter Cache Mirroring via Hardware Engines
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Solution Overview
Problem
Storage adapters often act as a performance bottleneck in computer systems, particularly with the increasing popularity of solid state drives (SSDs), necessitating a method and controller for optimizing storage adapter performance while minimizing firmware operations and maintaining essential functions like Write Caching and RAID operations.
Innovation Solution
A method and controller that implement cache data and cache directory mirroring between dual adapters, utilizing hardware engines to minimize firmware operations by chaining hardware operations and eliminating the need for firmware interactions in certain modes, thereby optimizing storage adapter performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional storage adapter operations are used, then firmware operations are performed for cache data mirroring, but this increases I/O operation time and reduces storage adapter performance
Solution Approach 1:
The patent replaces firmware-based operations with hardware-based operations. Specifically, hardware engines perform cache data and directory mirroring between dual storage adapters, eliminating the need for firmware intervention in these operations. This substitution of hardware for firmware directly reduces I/O operation time and improves storage adapter performance by handling mirroring operations in parallel at the hardware level.
Solution Approach 2:
The patent implements preliminary action by pre-configuring dual storage adapters with mirrored cache memory and directory structures before I/O operations occur. The hardware engines are pre-programmed to automatically perform mirroring operations as data is written to or read from cache, eliminating the need for subsequent firmware processing and reducing overall I/O operation time.
2Reliability
If firmware operations are used for cache mirroring, then essential functions like Write Caching and RAID operations are maintained, but device complexity increases due to firmware intervention
Solution Approach 1:
The patent segments the storage adapter functionality into distinct hardware engines, each responsible for specific operations such as cache mirroring, directory mirroring, Write Caching, and RAID operations. This segmentation allows each hardware engine to be optimized for its specific function while operating independently, reducing the need for complex firmware coordination and lowering overall device complexity while maintaining reliability.
Solution Approach 2:
The patent implements self-service by enabling hardware engines to autonomously perform mirroring and cache management operations without requiring firmware intervention. The dual storage adapters automatically synchronize cache data and directories through hardware-based protocols, allowing the system to maintain Write Caching and RAID operations independently, thereby reducing firmware complexity while preserving essential functions.
3Speed
If dual adapters with cache mirroring are implemented, then I/O operation speed increases, but hardware complexity increases due to additional controllers and memory
Solution Approach 1:
The patent merges the functionality of dual storage adapters into a unified hardware architecture where both adapters share common control logic and communication protocols. The hardware engines in both adapters are synchronized through a standardized interface, allowing cache mirroring to occur efficiently while reducing the overall hardware complexity compared to completely independent dual adapter configurations. This merging approach maintains I/O speed benefits while simplifying the system architecture.
Data Source
AI summary
A method and controller for implementing storage adapter performance optimization with cache data and cache directory mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. One of the first controller or the second controller operates in a first initiator mode includes firmware to set up an initiator write operation building a data frame for transferring data and a respective cache line (CL) for each page index to the other controller operating in a second target mode. Respective initiator hardware engines transfers data, reading CLs from an initiator control store, and writing updated CLs to an initiator data store, and simultaneously sends data and updated CLs to the other controller. Respective target hardware engines write data and updated CLs to the target data store, eliminating firmware operations of the controller operating in the second target mode.