Storage Addressing via Embedded Codeword Encoding
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Solution Overview
Problem
Existing data storage systems are inefficient in utilizing storage space due to conventional addressing methods that require significant area for address information, reducing the effective storage area.
Innovation Solution
The implementation of a data storage device with a read/write head assembly and a read channel circuit that includes a missing symbols insertion circuit, codeword de-scramble circuit, address insertion circuit, and data decoder circuit to pad, de-scramble, and insert address information into encoded codewords, allowing for efficient data addressing and decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of information
If conventional addressing methods (cylinder, head, sector or LBA) are used, then data can be accurately located and retrieved, but the storage area dedicated to address information increases, reducing effective storage capacity
Solution Approach 1:
The patent extracts the address information from the traditional storage location and integrates it into the data encoding structure itself. By incorporating address bits within the codeword format (e.g., using shortened LBA with address bits embedded in the codeword), the system eliminates the need for separate address fields on the storage medium, thereby recovering storage capacity that would otherwise be dedicated to addressing.
Solution Approach 2:
The patent merges the address information with the data information by combining them into a unified encoded structure. The address bits are integrated into the codeword along with the data bits, creating a combined data-address unit that is stored as a single entity. This merging eliminates the separation between address and data storage spaces.
2Quantity of substance
If address information is removed from data sets before writing, then storage efficiency improves, but the system complexity increases due to additional processing circuits
Solution Approach 1:
The patent performs preliminary encoding of address information into the data structure before the data is written to storage. The address bits are pre-integrated into the codeword during the encoding process, so that when data is read back, the address information is already embedded and ready for processing. This preliminary action simplifies the overall system by preparing data in advance.
Solution Approach 2:
The patent introduces an intermediary encoding layer that serves as a mediator between the raw data and the storage medium. This encoding layer automatically handles the address integration, acting as a buffer that translates between the host's address space and the storage medium's optimized structure. The intermediary processing circuit implements this translation function.
3Area of stationary object
If logical block addresses are incorporated in encoding algorithms, then storage area for addresses is reduced, but decoding complexity increases
Solution Approach 1:
The patent segments the decoding process into distinct functional stages: address extraction, data extraction, and error correction. By dividing the decoding task into separate modules, the system can handle the complexity of extracting embedded address information without overwhelming the overall decoding process. The address bits are extracted as a separate step from data decoding.
Solution Approach 2:
The patent changes the parameters of the encoding algorithm to accommodate address information within the codeword structure. By modifying the codeword format to include address bits at specific positions, the system creates a structured encoding that can be systematically decoded. The parameter changes in the encoding algorithm directly enable address integration while maintaining decodeability through structured design.
Data Source
AI summary
Various embodiments of the present invention provide systems and methods for format efficient data storage. As an example, a data storage device is described that includes: a storage medium, a read/write head assembly, and a read channel circuit. The read/write head assembly is disposed in relation to the storage medium and operable to sense information corresponding to an encoded codeword. The read channel circuit is operable to receive the encoded codeword. The read channel circuit includes a missing symbols insertion circuit, a codeword de-scramble circuit, an address insertion circuit, and a data decoder circuit. The missing symbols insertion circuit, the codeword de-scramble circuit, and the address insertion circuit together are operable to pad a derivative of the encoded codeword with a plurality of symbols, to de-scramble the derivative of the encoded codeword, and to insert address information corresponding to the derivative of the encoded codeword to yield a modified encoded codeword. The data decoder circuit is operable to apply a data decoding algorithm to the modified encoded codeword to yield a decoded output.