Storage Apparatus Parallel CRC Calculation for Data Transfer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
When using cyclic redundancy check (CRC) for data guarantee codes, the operation result varies with the order of data pieces, making it difficult to improve data transfer performance, especially when multiple DMA controllers are involved in transferring concatenated data.
Innovation Solution
A storage apparatus with a channel control unit, storage device, and processor that specifies element data to operation units for partial code calculation, allowing the processor to calculate a sequence code for concatenated data, thereby improving data transfer performance by parallelizing CRC operations across multiple DMA controllers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single DMA controller is used to transfer multiple pieces of data, then the guarantee code can be calculated correctly, but the data transfer performance is limited
Solution Approach 1:
The patent divides the data transfer task into multiple segments, with each DMA controller handling a specific piece of data independently. Each operation unit calculates the guarantee code for its assigned data segment in parallel, eliminating the sequential bottleneck while maintaining code accuracy through coordinated processing.
Solution Approach 2:
The patent combines multiple DMA controllers into a coordinated system where each controller operates independently on its assigned data while contributing to the overall guarantee code calculation. The results from multiple controllers are merged to produce the final guarantee code for concatenated data.
2Productivity
If multiple DMA controllers are used to transfer multiple pieces of data in parallel, then data transfer performance improves, but the guarantee code calculation becomes complex due to order dependency
Solution Approach 1:
The system performs preliminary actions by having each DMA controller calculate and store its individual guarantee code before the final concatenation operation. This preliminary calculation simplifies the subsequent combination step, as controllers only need to exchange and combine their pre-calculated codes rather than performing complex sequential operations.
Solution Approach 2:
The patent introduces an intermediary mechanism where each DMA controller calculates its guarantee code independently and then exchanges results with other controllers. This intermediary step decouples the parallel calculation phase from the final combination phase, reducing complexity while maintaining accuracy.
3Productivity
If multiple operation units calculate guarantee codes independently in parallel, then data transfer performance improves, but maintaining data order becomes challenging
Solution Approach 1:
The patent assigns specific data pieces to specific operation units with fixed assignments, creating local responsibility for data order. Each operation unit knows its position in the sequence and processes data accordingly, maintaining global order through localized control while enabling parallel processing.
Data Source
AI summary
A storage apparatus includes a channel control unit, a storage device, and a processor. The channel control unit includes a plurality of operation units. The processor specifies, when receiving a request for read of a plurality of pieces of element data from a host computer, the plurality of pieces of element data to the plurality of operation units, respectively. The plurality of operation units respectively reads the plurality of pieces of element data from the storage device, calculates a plurality of partial codes that is a plurality of guarantee codes on the basis of the plurality of pieces of element data, and transmits the plurality of partial codes to the processor. The processor calculates, on the basis of the plurality of partial codes, a sequence code that is a guarantee code of sequence data including the plurality of pieces of element data which is concatenated.