Solid-State Storage Array Data Placement for Latency and Capacity
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Solution Overview
Problem
Solid-state storage systems face performance degradation due to high read latency and susceptibility to read disturb errors in quad-level cell (QLC) mode, which requires frequent data relocation to low latency portions programmed in single-level cell (SLC) mode to mitigate these issues without increasing storage capacity.
Innovation Solution
A storage controller identifies frequently read data and relocates it to a low latency portion of the storage device programmed in SLC mode, while less frequently read data is stored in a high latency portion programmed in QLC mode, based on characteristics like read count, timestamp, and error rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored in QLC mode to maximize storage capacity, then storage capacity is improved, but read latency increases and read disturb errors occur
Solution Approach 1:
The storage device is divided into two distinct portions with different programming modes: a first portion programmed in SLC mode for storing frequently read data with high reliability and low latency, and a second portion programmed in QLC mode for storing less frequently read data to maximize capacity. This local differentiation of quality allows each portion to optimize for its specific function, resolving the contradiction between capacity and reliability.
2Productivity
If data is frequently read from QLC mode storage, then data accessibility is improved, but read disturb errors increase causing data corruption
Solution Approach 1:
Frequently read data is specifically directed to the SLC-mode first portion of the storage device, which is immune to read disturb errors. This local quality assignment ensures that data requiring high accessibility does not suffer from read disturb corruption, as the SLC portion provides both fast read access and protection against this specific harmful effect.
Solution Approach 2:
The storage controller acts as an intermediary that monitors read patterns and dynamically determines which portion (first or second) should store specific data based on expected read frequency. This intermediary function prevents frequently accessed data from being placed in the QLC portion where it would be susceptible to read disturb errors, thereby eliminating the harmful effect before it can occur.
3Loss of time
If data is relocated between storage portions to optimize performance, then read latency is improved, but device complexity increases
Solution Approach 1:
The storage controller serves as an intermediary that manages data placement by monitoring read patterns and determining optimal storage portions. This centralized control simplifies the complexity by providing a single point of decision-making rather than requiring distributed intelligence across storage cells, while still achieving low latency for frequently accessed data through intelligent routing to the SLC portion.
4Speed
If SLC mode is used for all data storage, then read latency is reduced, but storage capacity decreases
Solution Approach 1:
The storage device implements local quality differentiation by programming only the first portion in SLC mode for high-speed access while programming the second portion in QLC mode for high capacity. This resolves the contradiction by allowing the system to achieve fast read speeds for frequently accessed data in the SLC portion while maintaining overall high storage capacity through the QLC portion, rather than requiring the entire device to be SLC mode.
Solution Approach 2:
The storage device is segmented into two functional portions: a first portion optimized for speed (SLC mode) and a second portion optimized for capacity (QLC mode). This segmentation allows each portion to specialize in its strength, enabling the system to achieve both fast read performance and high storage capacity simultaneously, rather than forcing a single-mode design that would compromise one or the other.
Data Source
AI summary
A storage array controller may receive data to be programmed to a solid-state storage device of a plurality of solid-state storage devices. The storage array controller may identify a type of the data and determine whether to program the data to a low latency portion of the solid-state storage device based on the type of the data. In response to determining to program the data to the low latency portion of the solid-state storage device, the storage array controller may program the data to the low latency portion of the solid-state storage device.