Storage Array Manager Priority Arbitration for Demand Paging
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Solution Overview
Problem
Current memory systems face challenges in managing concurrent access, particularly in scenarios like demand paging where simultaneous read and write operations are critical, leading to performance bottlenecks due to the inability to handle urgent requests with different priority levels effectively.
Innovation Solution
A memory device with a data storage array manager that enforces an operating contract between the memory device and the host, allowing for prioritization and management of pending commands based on contract terms, enabling read-while-write access and suspend capabilities to handle higher-priority processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a memory controller performs only one memory access operation at a time to avoid conflicts, then data coherency is assured, but system productivity decreases due to blocking during read/write operations
Solution Approach 1:
The patent segments memory access operations into different priority levels (interruptible vs. non-interruptible operations). By dividing operations into these segments, the system can perform high-priority read operations during low-priority write operations without causing data coherency issues, thus improving productivity while maintaining reliability.
Solution Approach 2:
The patent introduces dynamic priority management where the memory controller can switch between different operation modes based on real-time conditions. The system dynamically adjusts which operations can interrupt others based on priority levels, allowing simultaneous read-write access when appropriate and preventing conflicts when necessary, thereby resolving the contradiction between coherency and performance.
2Loss of time
If the host device sends requests to SD/MMC devices without halting current processes, then response time improves, but the internal software requires long time outs for maintenance operations and arbitration
Solution Approach 1:
The patent extracts the arbitration and maintenance functions from the SD/MMC internal software and relocates them to the memory controller hardware. This extraction eliminates the need for long software time outs and complex internal arbitration, allowing the host to send requests immediately without waiting for software processing, thus reducing time loss while simplifying the overall system architecture.
Solution Approach 2:
The memory controller acts as an intermediary between the host device and the SD/MMC card. It handles the arbitration and coordination of access operations at the hardware level, eliminating the need for complex software-based arbitration. This intermediary approach allows fast response times while reducing the complexity of software management.
3Reliability
If demand paging requests are queued until ongoing read/write operations complete, then data coherency is maintained, but the urgency of urgent requests is compromised and system performance decreases
Solution Approach 1:
The patent implements dynamic priority-based interruption where urgent demand paging requests can interrupt ongoing non-urgent write operations. The memory controller dynamically adjusts operation execution based on priority levels, allowing urgent reads to proceed immediately while maintaining coherency through controlled interruption mechanisms. This dynamic approach resolves the contradiction by enabling both coherency maintenance and urgent request handling.
Solution Approach 2:
The patent changes the parameter of operation priority from static to dynamic. By assigning different priority levels to different operations and allowing interruption based on these changing priorities, the system can maintain data coherency while rapidly responding to urgent demand paging requests. This parameter change enables simultaneous progress on multiple operations without compromising either coherency or urgency.
4Adaptability or versatility
If legacy mass storage commands coexist with demand paging and TCP/IP interactions on the same bus, then device versatility improves, but managing concurrent operations with various priority levels becomes complex
Solution Approach 1:
The patent segments different protocol operations into distinct priority levels and access modes. Legacy mass storage commands, demand paging operations, and TCP/IP interactions are managed as separate priority classes with defined interruption relationships. This segmentation allows multiple protocols to coexist on the same bus while simplifying management through clear priority-based rules that determine which operations can interrupt others.
Data Source
AI summary
Techniques for rendering the management of processes supported by a storage device are described. In particular, the efficient allocation of storage array processing resources when managing concurrent processes on a storage array is described.