Storage Array with Series-Connected Write Transistors
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Solution Overview
Problem
Existing storage arrays face challenges in achieving high density due to large cell areas necessitated by the need for multiple signal lines per cell, limiting scalability and efficiency.
Innovation Solution
A storage array structure with m rows and n columns, where storage cells share word and bit lines, and write transistors in adjacent rows are connected in series, reducing the need for separate connections and minimizing area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If each storage cell has separate signal line connections, then reading and writing operations can be performed, but the cell area becomes large and storage density is reduced
Solution Approach 1:
The patent merges the signal line connections by connecting the source of the write transistor in non-last rows to the drain of the write transistor in the last row of the same column, forming a series connection structure. This sharing of signal lines reduces the number of separate connections needed per cell, thereby reducing cell area while maintaining reading and writing operation capabilities.
Solution Approach 2:
The series-connected write transistors in adjacent rows share common signal lines, allowing a single signal line to serve multiple storage cells across different rows. This multi-functionality enables the same signal line to perform write operations for multiple cells sequentially, reducing the overall number of signal lines needed and minimizing cell area overhead.
2Ease of manufacture
If multiple signal lines are connected to each storage cell, then write operations can be performed, but the number of connections increases and area overhead is maximized
Solution Approach 1:
The patent combines multiple write transistor connections into a single series connection chain. The source of the write transistor in non-last rows is connected to the drain of the write transistor in the last row, merging what would traditionally be separate connections into a unified structure that reduces the total number of connections while maintaining write operation capability.
Solution Approach 2:
The patent extracts and eliminates unnecessary connection lines by utilizing the series connection structure. By connecting write transistors in sequence across rows, the design removes the need for separate individual connections to each transistor, thereby reducing device complexity and the number of connections required.
3Adaptability or versatility
If storage cells are arranged with full connections, then all operations can be performed, but storage density is limited
Solution Approach 1:
The patent merges connection resources across multiple storage cells by implementing a series connection structure for write transistors in adjacent rows. This sharing of connection lines reduces the total number of connections needed, allowing more storage cells to be packed into the same area, thereby increasing storage density while maintaining operation capability.
Solution Approach 2:
The patent utilizes the vertical dimension by connecting write transistors across rows in a series configuration. This vertical integration allows multiple cells to share horizontal connection resources, effectively utilizing three-dimensional spatial arrangement to increase storage density without sacrificing operational versatility.
Data Source
AI summary
The present disclosure provides a storage array including storage cells, write word lines, read word lines, write bit lines, and read bit lines. The storage cells are arranged in a horizontal and a vertical direction to form a matrix structure with m rows and n columns. The storage cell includes a read transistor and a write transistor. A drain of the read transistor is connected to one read bit line. A source of the read transistor is connected to one read word line. A gate of the read transistor is connected to a drain of the write transistor to form an intermediate storage node. A gate of the write transistor is connected to one write word line. A source of the write transistor of a storage cell in the last row of the storage array is connected to one write bit line. A source of the write transistor of a storage cell in a non-last row is connected to the intermediate storage node of an adjacent storage cell in the next row of the same column.