Storage Array Spillover Mode for Capacity Threshold Write Redirection

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Solution Overview

Problem

Traditional storage systems face inefficiencies in data management and reliability due to unnecessary write operations and lack of centralized control over storage processes, particularly in flash-based storage systems.

Innovation Solution

Implementing a direct-mapped flash storage system where higher-level processes, such as the operating system, manage data blocks directly without address translation by storage controllers, and utilizing non-volatile RAM as a buffer to improve latency and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Extent of automation

If storage controllers perform address translation and manage data blocks, then storage management is automated, but redundant write operations increase and efficiency decreases

Engineering Contradiction:
Improvestorage management automationVSAvoidstorage write efficiency
Core Design Contradiction:
Extent of automationVSProductivity

Solution Approach 1:

The patent extracts the address translation function from the storage controller and relocates it to the host system. The storage controller no longer performs address translation or manages data blocks, instead receiving direct logical addresses from the host and writing data directly to flash memory locations. This extraction eliminates redundant write operations while maintaining automated storage management at the host level.

Inventive Principle:
Principle #2Taking out (Extraction)

2Speed

If flash memory is used for storage, then access speed is improved, but wear from frequent write operations increases reliability issues

Engineering Contradiction:
Improvestorage access speedVSAvoidflash memory reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent implements preliminary action by having the host system prepare and translate all addresses before writing to flash memory. The host maintains a mapping of logical addresses to physical flash locations and performs address translation in advance, allowing the storage controller to write data directly to the correct locations without additional read-modify-write cycles. This preliminary address preparation reduces the number of write operations needed and minimizes flash memory wear.

Inventive Principle:
Principle #10Preliminary action

3Ease of operation

If storage controllers manage data blocks with address translation, then data management is simplified, but system complexity increases

Engineering Contradiction:
Improvedata management simplicityVSAvoidstorage system complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The patent introduces the host system as an intermediary between the user and the storage controller. The host performs address translation and manages the mapping between logical addresses and physical flash locations, acting as a mediator that simplifies the storage controller's function. The storage controller becomes a simple write device that receives data and addresses from the host and writes directly to flash memory, reducing overall system complexity despite adding management functions at the host level.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12596498B2Data spillover for storage arrays
Publication Date: 2026.04.07 PURE STORAGE INC
  • US12596498B2 patent drawing
  • US12596498B2 patent drawing
  • US12596498B2 patent drawing

AI summary

Data spillover for storage arrays, including: entering, by a source storage array, in response to determining that an amount of used capacity for the source storage array exceeds a first threshold, a spillover mode; redirecting, in response to the source storage array being in the spillover mode, write operations directed to the source storage array to a target storage array; and exiting the spillover mode by the source storage array, wherein exiting the spillover mode comprises updating data stored on the source storage array to reflect write operations redirected to the target storage array during the spillover mode.