Storage Array Transistor Segmentation for Driving Current
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Solution Overview
Problem
Existing dual-port memory storage arrays face limitations in driving current due to voltage constraints, which hinder further miniaturization and density improvement of the storage array.
Innovation Solution
A storage array design featuring memory cells with two memories, one P-channel field effect transistor, and two N-channel field effect transistors alternately connected, allowing the source of the P-channel transistor to be connected to the drain of an N-channel transistor, and the drain of the P-channel transistor to be connected to the source of another N-channel transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a 1T1R array with N-type transistor is used, then the structure is simple and manufacturing is easier, but the driving current is insufficient at advanced nodes due to voltage limitations
Solution Approach 1:
The patent divides the single transistor function into multiple transistors (one P-channel and two N-channel transistors) working together in a segmented configuration. This segmentation allows each transistor to contribute to the overall driving current while maintaining simple individual structures, thereby resolving the contradiction between ease of manufacture and sufficient driving current.
Solution Approach 2:
The patent merges multiple transistors (P-channel and N-channel) into a single memory cell structure that works together to provide the required driving current. By combining the strengths of different transistor types in a unified configuration, the design achieves both manufacturability and high driving current capability.
2Quantity of substance
If the transistor size is reduced to improve density, then the storage array density increases, but the driving current becomes insufficient due to voltage constraints
Solution Approach 1:
The patent changes the electrical parameters of the memory cell by introducing a P-channel transistor in conjunction with N-channel transistors. This parameter change enables the cell to achieve higher driving current at reduced sizes by optimizing the voltage utilization and current contribution of each transistor, thereby increasing density without sacrificing driving capability.
3Power
If the gate voltage is increased to improve driving current, then the driving current increases, but the voltage supply limitation at advanced nodes prevents further increase
Solution Approach 1:
The patent inverts the conventional approach by using a P-channel transistor (which operates with negative gate-source voltage) alongside N-channel transistors. This inversion allows the circuit to efficiently utilize the available voltage supply at advanced nodes, achieving high driving current without requiring higher voltage levels that would exceed supply limitations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the drive capability of the circuit when a high level is inputted, effectively addressing the insufficient driving current issue and enabling further improvements in storage array density.
Implementation Method 1
one P-channel field effect transistor and two N-channel field effect transistors alternately connected to the P-channel field effect transistor
Data Source
AI summary
The present disclosure provides a storage array including memory cells arranged in a matrix array, each memory cell includes two memories, one P-channel field effect transistor and two N-channel field effect transistors alternately connected to the P-channel field effect transistor; a source of the P-channel field effect transistor is connected to a drain of a N-channel field effect transistor, a drain of the P-channel field effect transistor is connected to a source of the N-channel field effect transistor, and the two memories are respectively connected to the source of the P-channel field effect transistor and the source of the N-channel field effect transistor. The present disclosure can improve the density of the storage array and reduce the requirement for the drive capability of the field effect transistor.