Storage Device Barrier Command Write Order Guarantee

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Solution Overview

Problem

Existing storage devices fail to guarantee the order of write requests without degrading host performance, as data is first stored in a buffer memory before being written to nonvolatile memory, leading to potential losses in case of power failure or system crashes.

Innovation Solution

A storage device that receives barrier commands from a host, merges and programs data sequentially to nonvolatile memory, verifies program completion, and maps data as valid or invalid based on completion status, ensuring write order without waiting for each write operation to finish.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is first stored to buffer memory then to nonvolatile memory, then storage performance is improved, but write order is not guaranteed

Engineering Contradiction:
Improvestorage performanceVSAvoidwrite order guarantee
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces a barrier command that performs preliminary action by establishing a boundary marker in the command queue before data transfer. This barrier command is processed in advance to ensure that all data transfers before the barrier are completed before any data transfers after the barrier begin, thus guaranteeing write order while maintaining buffer memory performance benefits

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The barrier command acts as an intermediary element between the host and storage device, mediating the data transfer process. It inserts itself into the command queue and processes sequentially to create a clear division point, ensuring that data writes are ordered correctly without requiring the host to wait for each individual write operation to complete

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If host waits for data to be stored to nonvolatile memory before transferring next data, then write order is guaranteed, but host performance is degraded

Engineering Contradiction:
Improvewrite order guaranteeVSAvoidhost performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The storage device processes the barrier command in advance as a preliminary action, establishing the order boundary before the host finishes transferring all data. This allows the host to continue transferring data without waiting for previous writes to complete, while the storage device ensures order is maintained through the pre-processed barrier command

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The storage device performs self-service by autonomously processing barrier commands and managing data transfer ordering internally. The storage device takes responsibility for maintaining write order through its own internal barrier mechanism rather than requiring the host to actively wait and manage each transfer individually

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11741010B2Storage device storing data in order based on barrier command
Publication Date: 2023.08.29 SAMSUNG ELECTRONICS CO LTD
  • US11741010B2 patent drawing
  • US11741010B2 patent drawing
  • US11741010B2 patent drawing

AI summary

A method of programming data to a storage device including a nonvolatile memory device includes receiving first to third barrier commands from a host, receiving first to third data corresponding to the first to third barrier commands from the host, merging the first and second barrier commands and programming the first and second data to the nonvolatile memory device sequentially based on an order of the first and second barrier commands, verifying program completion of both the first and second data, mapping in mapping information of the first and second data when the programming of the first and second data is completed, and mapping out the information of both the first and second data when the programming of at least one of the first and second data is not complete, and programming the third data to the nonvolatile memory device after the mapping in or the mapping out.