Storage Buffer Address Redundancy for Silicon Area Reduction
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Solution Overview
Problem
Conventional semiconductor chips with logic unit duplication require duplicating storage arrays, which inefficiently uses more silicon area and does not effectively provide redundancy for address and control information without duplicating storage arrays.
Innovation Solution
The solution involves storing address and control information associated with data, calculating ECC or parity for redundancy, and checking for inconsistencies during data read operations to detect and correct errors without duplicating storage arrays, utilizing a system with delayed lock-step functional unit duplication and encoding/checking of data and address/control redundancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If storage arrays are duplicated to provide redundancy for address and control information, then reliability is improved, but silicon area increases
Solution Approach 1:
The patent segments the redundancy mechanism into two distinct parts: (1) duplication of logic units that generate and verify address/control information, and (2) a single storage array that is accessed by both logic units. This segmentation allows reliability to be improved through duplicated verification logic while avoiding the need to duplicate the large storage array, thus resolving the contradiction between reliability and silicon area.
Solution Approach 2:
The patent creates copies of the logic units (comparators, encoders, decoders) that work on address and control information, rather than copying the storage array itself. These copied logic units perform redundant verification of address and control signals, providing fault tolerance for the critical control paths without duplicating the data storage resources.
2Reliability
If logic units are duplicated to detect errors in address or control information, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent designs the duplicated logic units to perform multiple functions: they not only verify address and control information but also generate the actual read/write commands to the storage array. This multi-functionality reduces the need for separate verification and execution logic, thereby limiting the increase in device complexity while maintaining improved reliability through duplication.
3Reliability
If ECC or parity is applied to data, then reliability is improved, but storage area increases
Solution Approach 1:
The patent applies ECC or parity protection selectively and partially - specifically to the address and control information fields rather than to the entire data payload. This partial application provides sufficient protection for the critical control signals that determine data integrity, while avoiding the excessive storage overhead that would result from applying full ECC/parity to all stored data.
Data Source
AI summary
A system and method for detecting writes of data to errant locations in storage arrays. Address information and information redundant with address information is encoded and stored in proximity with data. Upon reading the stored data, the corresponding address information is decoded and compared to the address of the intended read. A mismatch indicates a possible write to an errant location.