Storage Device Cache Buffer Data Consistency Management

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Solution Overview

Problem

Existing storage devices face challenges in maintaining data consistency across memory blocks, particularly when handling write requests with the same logical address, which can lead to reliability issues and inefficient data management.

Innovation Solution

A storage device architecture that includes a memory controller with cache buffers and command list storages, which temporarily stores data based on attributes and ensures that previously stored data with the same logical address is flushed before new data is written, ensuring data consistency and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is stored directly in memory device without checking cache buffer, then write speed is improved, but data consistency is deteriorated

Engineering Contradiction:
Improvewrite speedVSAvoiddata consistency
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The system performs preliminary checking of cache buffers before writing data to the memory device. When a write request arrives, the controller first checks if data with the same logical address exists in any cache buffer, and if so, flushes it to the memory device beforehand. This preliminary action ensures data consistency without significantly impacting write speed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The cache buffer acts as an intermediary between the host and the memory device. It temporarily stores data with the same logical address before the memory device write operation, allowing the system to maintain data consistency while preserving fast write performance. The intermediary structure resolves the conflict between speed and reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If data with same logical address is stored in cache buffer, then data consistency is improved, but memory resource usage is worsened

Engineering Contradiction:
Improvedata consistencyVSAvoidmemory resource usage
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The system extracts and stores only the necessary information (data with same logical address) in the cache buffer, rather than storing all data. This selective extraction approach maintains data consistency while minimizing memory resource consumption by keeping only the specific data needed for consistency checking.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The cache buffer temporarily holds data with the same logical address only until it needs to be flushed to the memory device. After flushing, the cache buffer resources are recovered and can be reused for new data. This temporary storage and recovery mechanism maintains consistency while efficiently managing memory resources.

Inventive Principle:
Principle #34Discarding and recovering

3Adaptability or versatility

If multiple cache buffers are used to store data with different attributes, then data management flexibility is improved, but device complexity is worsened

Engineering Contradiction:
Improvedata management flexibilityVSAvoidcontroller complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The cache buffer is divided into multiple segments or buffer regions (first cache buffer, second cache buffer) that can store data with different attributes separately. This segmentation allows flexible data management by organizing data according to their characteristics while maintaining a relatively simple controller structure through systematic management of each segment.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11693589B2Storage device using cache buffer and method of operating the same
Publication Date: 2023.07.04 SK HYNIX INC
  • US11693589B2 patent drawing
  • US11693589B2 patent drawing
  • US11693589B2 patent drawing

AI summary

A storage device capable of maintaining consistency of data for the same address may include a memory device including a plurality of memory blocks, a buffer memory device including a plurality of cache buffers temporarily storing data previously received from a host, and a memory controller configured to receive a write request and a write data from the host and configured to control the buffer memory device and the memory device to store a previously received data, stored in one of the plurality of cache buffers with a logical address that matches a logical address of the write data, in the memory device before the write request is processed.