Storage Cache and GC Buffer Access for Lower Tail Latency
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Solution Overview
Problem
Storage devices experience long latency during garbage collection operations due to the need to copy valid data to a second erase block, leading to increased tail latency in accessing storage media.
Innovation Solution
Implementing a storage device with a device cache and a garbage collection buffer, utilizing metadata to determine access paths and employing priority queues to manage requests, thereby reducing latency by processing requests through the cache or buffer instead of directly accessing storage media.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If garbage collection operations copy valid data to a second erase block, then storage media availability is improved, but access latency increases
Solution Approach 1:
A buffer is introduced as an intermediary component between the storage media and the host system. During garbage collection operations, valid data is copied to the buffer instead of directly to a second erase block, allowing the storage media to be erased and reused. The buffer temporarily holds this data, preventing direct access delays and reducing tail latency while maintaining data availability.
2Reliability
If reserved space is allocated for garbage collection operations, then garbage collection reliability is improved, but storage capacity decreases
Solution Approach 1:
The buffer serves multiple functions: it acts as a temporary storage during garbage collection operations, a cache for frequently accessed data, and an overflow buffer when the device cache is full. This multi-functionality allows the system to perform reliable garbage collection without dedicating separate reserved space, thereby maximizing storage capacity while maintaining operational reliability.
Solution Approach 2:
The system uses the device cache and buffer resources already present in the storage device to support garbage collection operations, rather than allocating additional reserved space. The buffer leverages existing memory resources to temporarily hold valid data during erasure operations, enabling the system to serve its own garbage collection needs without external dedicated space.
3Speed
If device cache is used to reduce access latency, then access speed is improved, but device complexity increases
Solution Approach 1:
The buffer is designed to share physical memory resources with the device cache, merging two functional components into a unified memory structure. The buffer utilizes available cache memory when the cache is not fully occupied, eliminating the need for completely separate memory allocations. This integration reduces overall device complexity while maintaining fast access speeds through intelligent memory management.
Data Source
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AI summary
A device may include a storage medium, a cache medium, a buffer medium, and at least one control circuit configured to perform one or more operations including receiving a first request to access the storage medium, accessing, based on the first request, the cache medium, copying, from a portion of the storage medium to the buffer medium, data, modifying, based on the copying, an availability of the at least a portion of the storage medium, receiving a second request to access the storage medium, and accessing, based on the second request, the buffer medium. The one or more operations may include determining a location of data associated with the second request, and accessing, based on the determining, the buffer medium. The one or more operations may include receiving information about a location of data associated with the second request, and accessing, based on the information, the buffer medium.