Storage Capacitance Lines in Display Devices
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional liquid crystal display devices experience high power consumption in data lines due to parasitic capacitance generated by overlapping storage capacitance lines and data lines, leading to increased energy usage.
Innovation Solution
The storage capacitance lines are arranged parallel to the data lines on the same plane, made of the same material, and designed to minimize overlap with data lines, reducing parasitic capacitance and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If storage capacitance lines are arranged to intersect with data lines in a common plane, then storage capacitance can be formed effectively, but parasitic capacitance increases causing higher power consumption
Solution Approach 1:
The patent transitions storage capacitance line arrangement from a planar intersection configuration to a three-dimensional stacked configuration. Storage capacitance lines are placed on the same plane as scanning lines (first plane) while data lines are on a different plane (second plane), creating vertical separation that eliminates parasitic capacitance between storage capacitance lines and data lines while maintaining effective storage capacitance formation between storage capacitance lines and pixel electrodes.
Solution Approach 2:
The patent extracts the storage capacitance line arrangement from the data line plane, separating it into a distinct first plane. This extraction removes the harmful interaction (parasitic capacitance) between storage capacitance lines and data lines while preserving the essential function of storage capacitance formation through the overlapping relationship with pixel electrodes.
2Adaptability or versatility
If storage capacitance lines overlap with data lines, then routing flexibility is improved, but parasitic capacitance is generated increasing power consumption
Solution Approach 1:
The patent resolves the routing flexibility issue by utilizing the third dimension (vertical stacking). Storage capacitance lines are routed on the first plane with scanning lines, while data lines are routed on the second plane, allowing both to maintain their respective routing paths without harmful overlap, thereby preserving routing flexibility while eliminating parasitic capacitance-induced energy loss.
3Productivity
If data lines are driven numerous times for each scanning line, then complete image writing is achieved, but power consumption increases significantly
Solution Approach 1:
The patent converts the potentially harmful parasitic capacitance effect into a beneficial configuration by strategically placing storage capacitance lines on the first plane to overlap with scanning lines rather than data lines. This configuration maintains the necessary multiple data line driving operations for complete image writing while eliminating the harmful energy loss, as the storage capacitance lines now overlap beneficially with scanning lines which have different electrical characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces power consumption in data lines while maintaining effective storage capacitance, enhancing the aperture ratio and overall display efficiency.
Implementation Method 1
a plurality of storage capacitance lines disposed substantially in parallel with the data lines, each of the storage capacitance lines having a portion overlapping with a portion of the pixel electrode
Data Source
AI summary
A display device includes a substrate having a display area; a plurality of scanning lines and a plurality of data lines, arranged in the display area over the substrate, wherein the data lines extend substantially orthogonally to the scanning lines; a plurality of switching elements each connected to respective one of the scanning lines and to respective one of the data lines; a plurality of pixel electrodes each connected to respective one of the switching elements; and a plurality of storage capacitance lines disposed substantially in parallel with the data lines, each of the storage capacitance lines having a portion overlapping with a portion of the pixel electrode, the storage capacitance lines being disposed on a plane on which the data lines are disposed and being made of the same material as the data lines.