Storage Capacitor Parasitic Capacitance Reduction Antenna Aperture
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Solution Overview
Problem
In RF antenna apertures, the limited space between antenna elements makes it difficult to route circuitry and electrical wiring, leading to congestion and complexity, especially as higher frequencies require closer element spacing without proportional reductions in wiring trace widths and circuit element distances.
Innovation Solution
A storage capacitor design with multiple conductive layers, where the top and bottom layers are at the same voltage, reducing parasitic capacitance and allowing for a more compact footprint by using a third metal layer connected to the gate metal bottom plate, thereby decreasing the overall size of the storage capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pitch of antenna elements is reduced to increase the number of elements, then the antenna aperture can accommodate more elements, but the space for routing circuitry and wiring becomes insufficient
Solution Approach 1:
The patent combines the storage capacitor with the antenna element structure by integrating it into the same substrate and using shared conductive layers. The storage capacitor is formed using the gate metal layer, source/drain metal layers, and additional metal layers that are already part of the antenna element fabrication process, eliminating the need for separate capacitor structures and reducing routing complexity
Solution Approach 2:
The patent makes the metal layers serve multiple functions: the gate metal layer and source/drain metal layers are used both for the transistor structure and for forming the storage capacitor electrodes. This multi-functionality reduces the total number of required metal layers and simplifies the overall device structure, making it easier to route signals with reduced complexity
2Reliability
If the wiring trace widths and circuit element distances are maintained at higher frequencies, then signal integrity is preserved, but the space between antenna elements becomes insufficient
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked structure by forming the storage capacitor with multiple metal layers at different heights on the same substrate. This vertical stacking allows the circuit elements to occupy less horizontal space while maintaining adequate trace widths and spacing for signal integrity at higher frequencies
3Quantity of substance
If a conventional storage capacitor structure is used, then the capacitor provides sufficient storage capacity, but it occupies excessive space between antenna elements
Solution Approach 1:
The patent nests the storage capacitor structure within the antenna element fabrication process by using the same metal layers and substrate. The capacitor is formed by stacking conductive layers vertically, with the gate metal layer, source/drain metal layers, and additional metal layers nested together to form a compact three-dimensional structure that provides sufficient capacitance in a minimal footprint
Solution Approach 2:
The patent achieves high capacitance in a small footprint by transitioning to a three-dimensional stacked structure. Multiple metal layers are stacked vertically at different heights, creating a compact capacitor that occupies minimal horizontal space while providing sufficient storage capacity through the increased effective area in the vertical dimension
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces parasitic capacitance, allowing for a smaller storage capacitor footprint and simplifying the routing of circuitry, improving RF performance and reducing the complexity of the antenna layout.
Implementation Method 1
reduce parasitic capacitance produced between the storage capacitor and the conductive layer on the second substrate
Data Source
AI summary
A storage capacitor and method for using the same in an antenna aperture are described. In one embodiment, an antenna comprises a physical antenna aperture having first and second substrates forming an array of radio-frequency (RF) radiating antenna elements that are controlled and operable together to form a beam for the frequency band for use in holographic beam steering, wherein each of the antenna elements is coupled to a circuit to supply a voltage to the said each antenna element and a storage capacitor formed with a plurality of conductive layers (e.g., metal layers) on a first substrate, wherein top and bottom conductive layers of the plurality of conductive layers are at a first voltage that is equal to a second voltage on a conductive layer (e.g., a metal layer) of the second substrate to reduce parasitic capacitance produced between the storage capacitor and the conductive layer on the second substrate.