Storage Capacitor Placement for Parasitic Capacitance Reduction
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Solution Overview
Problem
Conventional light emitting displays suffer from decreased picture quality due to parasitic capacitance, which varies the voltage applied to pixels, especially when the anode and data line, and storage capacitor are formed close together, leading to increased parasitic capacitor capacity and voltage variance.
Innovation Solution
The solution involves forming a storage capacitor between the anode of an organic light emitting device and an adjacent data line, effectively connecting parasitic capacitors to different data lines, thereby minimizing voltage variance by distributing the current across these capacitors, ensuring they have one tenth or less capacity than the storage capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the anode and data line, and storage capacitor are formed close together to secure sufficient aperture ratio, then the aperture ratio is improved, but the parasitic capacitor capacity increases causing decreased picture quality
Solution Approach 1:
The patent divides the parasitic capacitance effect into two separate capacitors (first parasitic capacitor CP1 between storage capacitor and data line, second parasitic capacitor CP2 between anode and data line) and connects them to different data lines (nth data line Dn and (n+1)th data line Dn+1 respectively). This segmentation allows the voltage variations from parasitic capacitors to be distributed across different data lines, minimizing the overall voltage variance in any single pixel while maintaining close spacing for aperture ratio.
2Area of moving object
If the anode and data line, and storage capacitor are formed close together, then the aperture ratio is improved, but the voltage variance increases due to increased parasitic capacitor capacity
Solution Approach 1:
The patent segments the voltage variance problem by connecting parasitic capacitors to different data lines. The first parasitic capacitor CP1 is connected to the nth data line Dn while the second parasitic capacitor CP2 is connected to the (n+1)th data line Dn+1. This segmentation distributes the voltage fluctuations across different data lines, preventing them from accumulating in a single pixel and thereby minimizing voltage variance.
Solution Approach 2:
The patent introduces an intermediary approach by using different data lines as mediators for the parasitic capacitors. Instead of both parasitic capacitors being connected to the same data line, the invention uses the nth data line Dn and (n+1)th data line Dn+1 as separate intermediaries, which helps isolate and minimize the voltage variance effect on any single pixel.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration minimizes voltage variance across pixels, enhancing picture quality by reducing the impact of parasitic capacitors, resulting in more uniform brightness and improved representation of high gradations.
Implementation Method 1
a storage capacitor to store a voltage corresponding to a data signal supplied from the nth data line when the switching transistor is turned on
Implementation Method 2
the self-emissive light emitting display utilizes electron-hole recombination in a fluorescent layer to emit light
Implementation Method 3
The emitting layer, which comprises at least a light emitting layer, may also include an electron transport layer interposed between the emitting layer and the cathode and a hole transport layer interposed between the emitting layer the anode
Data Source
AI summary
A light emitting display including a plurality of scan lines; a plurality of data lines crossing the scan lines; a plurality of pixels defined by the scan lines and the data lines; and a light emitting device formed on a pixel and comprising a first electrode and a second electrode. A pixel connected to an nth data line includes a switching transistor that turns on in response to a selection signal supplied from a scan line; a storage capacitor to store a voltage corresponding to a data signal supplied from the nth data line when the switching transistor is turned on; and a driving transistor to supply a current corresponding to the voltage stored in the storage capacitor to the first electrode. The storage capacitor is formed between the first electrode and an (n+1)th data line.