Layout structure of storage cell and manufacturing method thereof
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Solution Overview
Problem
The existing electrical fuses in integrated circuits (ICs) are vulnerable to reverse engineering, which compromises the security of proprietary information stored in them, as the resistance changes during programming can be reverse-engineered, allowing unauthorized access to embedded manufacturer codes.
Innovation Solution
The solution involves forming a layout structure of a memory array with multiple fuses in different metal layers, where programming current randomly burns or fuses these fuses, ensuring that the burnt fuses do not all reside in the same metal layer, making it difficult to reverse-engineer the manufacturer's proprietary code by distributing the burnt fuses across different layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple fuses are placed in different metal layers to enhance security, then the security against reverse engineering is improved, but the device complexity increases
Solution Approach 1:
The patent applies dimensionality change by distributing fuses across multiple metal layers (vertical dimension) rather than placing them all in a single layer. This spatial distribution in the Z-dimension (layer depth) makes reverse engineering more difficult because an attacker would need to analyze multiple layers to reconstruct the complete fuse map, thereby enhancing security while managing complexity through systematic multi-layer integration.
Solution Approach 2:
The fuse array is segmented across multiple metal layers, with different portions of the fuse matrix distributed in different layers. This segmentation prevents an attacker from obtaining the complete fuse configuration by examining a single layer, as the proprietary information is fragmented across multiple spatial locations and layers, requiring comprehensive analysis of all layers to reconstruct the full picture.
2Object-affected harmful factors
If fuses are distributed across different metal layers, then reverse engineering difficulty increases, but the manufacturing process complexity increases
Solution Approach 1:
The patent employs universal fuse link structures and standardized inter-layer connections that can be replicated across multiple metal layers using the same fabrication processes. This multi-functionality approach allows the same manufacturing techniques to be applied repeatedly for creating fuses in different layers, reducing the incremental complexity of adding multi-layer support while maintaining the security benefits of distributed fuse placement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the security of the fuse array in ICs by making it challenging to obtain proprietary information through reverse engineering, as the distribution of burnt fuses across different metal layers obscures the programming state, thereby protecting the embedded data.
Implementation Method 1
programming current randomly burns or fuses the plurality of fuses
Data Source
AI summary
A method of forming a storage cell includes: forming a transistor on a semiconductor substrate; forming a plurality of fuses in at least one conductive layer on the semiconductor substrate to couple a connecting terminal of the transistor; forming a bit line to couple the plurality of fuses; and forming a word line to couple a control terminal of the transistor.