Storage Chiplet Computing to Reduce Interconnect Bandwidth Load
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Solution Overview
Problem
The bandwidth and power consumption pressures on the chiplet interconnection interface of storage chiplets are increasing due to the rising data operation demands in computer systems.
Innovation Solution
Incorporating a calculation module within the storage chiplet to perform data reading, operation, and storage operations internally, reducing the need for the chiplet interconnection interface to handle these tasks externally.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data operations are performed externally through the chiplet interconnection interface, then data processing capability is improved, but bandwidth pressure and power consumption of the interconnection interface increase
Solution Approach 1:
The patent combines the calculation module with the storage chiplet to form an integrated unit. The calculation module is physically merged with the storage chiplet, allowing data operations to be performed locally within the same chiplet without requiring external communication through the interconnection interface. This merging eliminates the need for separate data transmission between storage and computation units, thereby reducing bandwidth pressure and power consumption of the interconnection interface while maintaining data processing capability.
2Productivity
If data operations are performed externally through the chiplet interconnection interface, then data processing capability is improved, but bandwidth pressure of the interconnection interface increases
Solution Approach 1:
The calculation module is integrated within the storage chiplet, creating a unified processing unit. This integration allows the chiplet to perform data operations internally using locally stored data, eliminating the need to transfer data in and out through the interconnection interface. As a result, the volume of data transmitted through the interface is significantly reduced, alleviating bandwidth pressure while preserving full data processing functionality.
3Device complexity
If only storage function is implemented in storage chiplet, then device simplicity is maintained, but data processing efficiency decreases
Solution Approach 1:
The storage chiplet is enhanced with multi-functionality by integrating a calculation module alongside the storage function. This allows the same chiplet to perform both data storage and data processing operations, eliminating the need for separate computation units. The chiplet structure remains relatively simple while gaining enhanced data processing efficiency through this functional expansion.
Data Source
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AI summary
Embodiments of the present invention provide a storage chiplet, a data processing method, and a computer system. The storage chiplet comprises: a chiplet interconnect interface, computing modules, and storage modules. The chiplet interconnect interface is used for receiving a data processing command sent to the storage chiplet and transmitting the data processing command to the computing modules. Each computing module is used for reading target data from a corresponding storage module on the basis of the data processing command; performing computation on the target data on the basis of the data processing command to obtain a computation result; and on the basis of the data processing command, enabling the computation re suit to be stored in the storage module. Each storage module is used for storing data. According to the embodiments of the present invention, the computing modules are provided in the storage chiplet, so that the data reading, computation and computation result storage are implemented in the storage chiplet, preventing the data reading and storage from being implemented by the chiplet interconnect interface, thus reducing the bandwidth pressure and power consumption of the chiplet interconnect interface of the storage chiplet.