Storage Comparator Circuit Layout for Reduced Memory Chip Area
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Solution Overview
Problem
Existing semiconductor memory comparators have complex internal structures and large chip areas, leading to increased costs due to the use of latch and XNOR gate circuits, which occupy excessive space when used extensively.
Innovation Solution
A storage comparison circuit device comprising a latch with a transmission gate, inverter, and tri-state gate, and a comparator with specific control signals to enable or disable these components, reducing chip area and calculation complexity by using modular structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If latch and XNOR gate circuits are used in existing comparators, then data storage and comparison functions are achieved, but chip area increases and device complexity increases
Solution Approach 1:
The patent merges the latch and comparator functions into a single integrated storage comparator circuit. The latch circuit and comparison logic are combined such that the same circuit elements perform both storage and comparison operations, eliminating the need for separate latch and XNOR gate modules, thereby reducing chip area while maintaining full functionality
Solution Approach 2:
The storage comparator circuit is designed to perform multiple functions using the same hardware resources. The latch circuit can store data and simultaneously participate in comparison operations, making the circuit elements multi-functional rather than dedicated to single tasks, which reduces the overall circuit complexity and area requirement
2Reliability
If latch and XNOR gate circuits are used in existing comparators, then data storage and comparison functions are achieved, but device complexity increases
Solution Approach 1:
The patent combines the latch and comparator circuits into a unified storage comparator structure. The comparison logic is integrated with the latch circuit elements, reducing the total number of discrete components and simplifying the overall device architecture while preserving both storage and comparison capabilities
Solution Approach 2:
The storage comparator is divided into functional modules with clear interfaces: a first latch for storing first data, a second latch for storing second data, and comparison logic that operates on these latched values. This modular segmentation allows each component to be optimized independently while reducing overall complexity through standardized interfaces
Data Source
AI summary
Embodiments provide a method for data storage and comparison, a storage comparison circuit device, and a semiconductor memory. The storage comparison circuit device includes a latch and a comparator. The latch is configured to latch inputted first input data and output first output data and second output data. The first output data are the same as the first input data, whereas the second output data are different from the first input data, wherein the first output data and the second output data are respectively inputted into the comparator. The comparator is configured to receive second input data, the first output data and the second output data, and to output a comparison result. By using modular structures of the latch and the comparator, device data can be simplified for the latch and the comparator, chip area can be reduced, calculation amount can be reduced, and efficiency of data comparison can be improved.